I have a development board with an EP4CE6E22C8 FPGA.
I have the following verilog code in Quartus Prime:
module Test(out); output [7:0] out; assign out = 8'b00111100; endmodule
The pin planner has been configured as pointed by the schematic. The problem is that 0 means on and 1 means off. I think this is a strange behaviour since the typical one is 1=on and 0=off.
Anybody knows if there is any option (in pin planner, quartus prime or whatever) to change this behaviour?