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Stratix 10 H-Tile 100G Ethernet example design creates broken constraints

AFies
Beginner
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Hello,

I recently tried to set up the S10 100G Ethernet MAC hard IP (H-Tile) on my S10 1SG280HU1F50E2VG. I used the example design as a basis and changed the necessary assignments and configuration for my device.

Now the design fails timing by a serious margin, which looks like the constraints are not working.

The issue is this launch clock:

av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|tx_clkout|ch0

When the timing analyzer loads, it reports almost all constraints that were generated by the example design as erroneous (i.e., no clock found). I did not change any entity names.

set CORECLK         [get_clocks av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|tx_clkout|ch0]
set CORECLK         [get_clocks av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|*tx_clkout|ch0]
set CORECLKRX       [get_clocks av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|*rx_clkout|ch0]
set RX_CLK0         [get_clocks av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set RX_CLK1         [get_clocks av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set TX_CLK0         [get_clocks av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]
set TX_CLK1         [get_clocks av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]

 However, the nodes are definitely present. When I enter the same get_clocks command in the tcl shell of the timing analyzer, it returns something not empty.

I already tried to manually create the two ATX PLL cores and use them instead of the core-generated ones, with exactly the same result.

How do I properly constrain this core? Unfortunately the user guide for this core contains almost zero information about constraints.

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