Stratix 10 MX HBM2 Addressing with Avalon-MM user side interface

[s10M]

Hello,

I am currently trying to create a design that uses the HBM2 Avalon-MM user-side interface. 

I have started with this Intel Forum design, which has worked and has been quite helpful. 

However, when I am trying to adapt the design to my needs, I am faced with a few confusions.

In particular, I am using a msGDMA and a write master to convert an Avalon stream to an Avalon MM format. The write DMA master is interfaced with the HBM2. I have done something similar and instantiated a read DMA master, interfaced to the same channel (and pseudo-channel) of the HBM2. 

I am monitoring the read and writes of the DMAs on SignalTap.  My writes seem to work perfectly. And at a given incrementing address, 256-bit writes are captured by the HBM2.

Once this is complete, the read master is triggered. Unfortunately, the read master doesn't show the data that I would expect.  Writing a fixed pattern on addresses  0x0-0xFFF would only yield some of the reads to have the same constant pattern, while other reads have some erroneous bits. 

My question is that if I was to write on address 0 a particular 256-bit word, why is that when I am reading address 0, not all the 256 bits are as expected? 

Is there something I am overlooking with regards to addressing in the HBM2? The documentation currently has very limited support for Avalon MM use cases.

Another puzzling thing is that when I connect a write DMA to one pseduo-channel and the read DMA to another pseduo-channel of the same HBM2 channel, I get completely different reads from what I had written? Is this expected behavior? Can one not access the memory of the same channel via either of the pseduo-channels? 

Thank you for the help

[AdzimZM_Intel]

Hello,

I think you can refer to this KDB:

https://www.intel.com/content/www/us/en/support/programmable/articles/000086781.html

Please let me know if that help.

Regards,

Adzim

[s10M]

Hello Adzim,

Thank you for directing me to the KDB.

Unfortunately, I have migrated my design to Quartus 21.1 but the problem still persists. 

i.e. when both read and write Avalon masters are connected to the HBM2, reads are not as expected when reading a particular address.  A few bits are always incorrect in consecutive reads. 

Furthermore, when the two Avalon masters are connected to different pseuo-channels (of the same channel) of the HBM2, the reads are completely different. 

Would appreciate it if you could verify if this is expected behavior.

Thank you. 

[AdzimZM_Intel]

Hello,

I would encourage you to use the workaround from the KDB.

Please let me know the result of the testing.

Thanks,

Adzim

[s10M]

Hello Adzim,

One of the workarounds suggested by the KDB was to use Intel® Quartus® Prime Pro Edition software version 21.1 or higher, which I have done.

Unfortunately, the problem still persists. 

i.e. when both read and write Avalon masters are connected to the HBM2, reads are not as expected when reading a particular address.  A few bits are always incorrect in consecutive reads. 

Furthermore, when the two Avalon masters are connected to different pseuo-channels (of the same channel) of the HBM2, the reads are completely different. 

Would appreciate it if you could verify if this is expected behavior.

Thank you. 

[AdzimZM_Intel]

Hi Sir,

I would like to replicate the issue from my side.

Maybe you can share a simple design that can reproduce the issue and provide the step as well.

Thanks,

Adzim

[AdzimZM_Intel]

Hello Sir,

Do you have any feedback regarding to my previous comment?

Thanks,

Adzim

[AdzimZM_Intel]

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.