Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

[LHinC1]

Hi Altera AE ,

    We are working on a design on Stratix 10 using PHYLite library.

    We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any problem in Arria 10.

    In Stratix 10, the waitrequest signal was stuck at high all the time

    before we issue any command to the avalon bus after reset.

    We solved this by issuing a number of dummy write commands to avalon bus, the waitrequest signal returns to 0.

    We got help from Altera AE on this issue, and now we see another issue thus I raise a post here.

    After solving the waitrequest issue, we continue to read the basic information from the avalon bus,

    we can see the readdata_valid pulse in signal tap but avl_readdata is always 0

    when we read the address 0x05000024.

    We don't see anything wrong in the RTL, but we see that the avl_readdata is always 0.

    Until we make an irrelevant change to the code, the avl_readdata becomes normal again such that the readdata_valid looks the same as what it is when the avl_readdata is 0.

    It is so weird, we spent a couple of days on this.

    Please help us on this, we have been stuck on the avalon bus communication for 3 months.

    FYI : we are using quartus version 19.3

Thanks,

Samson

[IntelSupport]

Hi Samson,

Thank you for reaching out to Intel Forum. My name is Rashmi.

can you please provide me with project to reproduce the issue at my end also the screen shots of signal taps of the signals .

Regards,

Rashmi

[LHinC1]

Hello Rashmi,

Thank you for your support.

I have attached my code and the screenshots.

Thanks,

Samson

[Rashmi1]

Thank you. I will work on reproducing the issue and get back to you shortly.

[LHinC1]

Hello Rashmi ,

Excuse me, it is very urgent for us, do you have any update?

Thank you so much.

Samson

[Rashmi1]

Hi Samson,

It seems like the write transaction isn’t completing prior to the read transaction.

How are you verifying if transfer of all the write data for the write transaction?

Thanks,

Rashmi

[LHinC1]

Hello Rashmi,

We are accessing the PhyLite through the Avalon bus,

We read the indirect address from the address 0x05000024.

It does not require any write command before reading data, is it correct?

I attach the table copied from Phy Lite user guide.

We did the same thing in our last Arria 10 design.

I encounter this problem when I move our design to Stratix 10 device.

Thanks,

Samson

[Rashmi1]

Hi Samson,

Do you mind to share what’s the irrelevant code change to fix the avl_data 0?

For this avl_data is 0, I would think we can check the pin assigned by checking the correct lane or pin addresses that are assigned correctly. You can refer to this PHYlite wiki page to get the correct addresses.

Thanks,

Rashmi

[LHinC1]

Hello Rashmi,

We just changed a single line in our design, then we get the following result.

I attached a picture "SignalTap.png".

We just changed one single line in a state machine that interfaces with the avalon bus.

The difference is shown in "before (failed).png" and "after (working).png".

I also attached my code "TC4200ST_L_19_3_20200728.qar", this one is the working one.

Thanks,

Samson

[Rashmi1]

also, can you reproduce the issue in simulation ?

[LHinC1]

Hi Rashmi,

We normally do a simulation with basic building blocks.

We haven't done any simulation with the whole design, this would be very time-consuming.

Thanks,

Samson

[Rashmi1]

HI Samson,

Thank you for providing all the required information. I have been consulting with our Engineering team for further debug . Based on the issue criticality we decided to escalate the issue for our Factory Apps team to further debug, we suspect something more going on which requires in depth review.

I will keep you updated .

Thanks,

Rashmi

[Rashmi1]

Hi Samson,

Please review the KDB below:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/emif/2019/warning-332035---no-clocks-found-on-or-feeding-the-specified-sou.html

let me know if this helps.

Thanks,

Rashmi

[LHinC1]

Hello Rashmi,

Yes, our distributor FAE has provided this workaround to us on Quartus version 19.3,

we tried it already, it doesn't help, the result is the same.

Thanks,

Samson

[Rashmi1]

Thank you for try the workaround suggestion. As i mentioned factory Apps Engineer is working on the issue. I will provide you an update as we make progress.

[Rashmi1]

I do find this INI below in the design, can I know what’s the use of the INI? I would think this INI will no impact on this issue, just for understanding.

bypass_vid_when_pmbus_mode_master_all_slave_address_3f = on i8XOhQg3u5 = 9WdkQrX0sx

Also, the customer can run the design in the A10 board while migrating the design to S10, they faced this issue.

Can I know which the Avalon fie that the you modified? Please point me there. Thanks.

[LHinC1]

Hello Rashmi,

I think the ini file was created by Quartus Prime software. We encountered an issue at the beginning regarding the Stratix 10 Smart VID. We got an answer in the forum and then we followed the solution provided in Altera forum.

We did not copy the PHY Lite library code from our Arria 10 design, as we saw there are lots of differences between the PHY Lite files generated in Quartus 16.0 for our Arria 10 design and the PHY Lite files generated in the Quartus Prime 19.3. So we regenerated all the necessary files in Quartus Prime 19.3 for our Stratix 10 project.

By the way, did you reproduce the same situation as we saw?

Thanks,

Samson

[Rashmi1]

Hi Samson,

Can you please try on the design to a new Quartus version instead of Quartus19.3? This is to check any fix is done in engineering on the new Quartus version or not. 

Thanks,

Rashmi

[LHinC1]

Hello Rashmi,

OK, we will do it on v20.2.

By the way, we would like to do simulation on v19.3, however we could not find any user guide of ModelSim-Intel for quartus v19.3, the user interface differs a lot from the previous version.

Thanks,

Samson

[Rashmi1]

Here are few links:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/simulation/modelsim/simulation-nativelink-howto.html

Latest document : Intel® Quartus® Prime Design Suite 18.0

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_gs_msa_qii.pdf

[LHinC1]

Hello Rashmi,

Thank you for the document.

We read these 2 PDF files before, but it seems they are only valid for v18.0.

The user interface has changed a lot in v19.3 and v20.2.

Is there any document updated which is for v20.2 ?

Thanks,

Samson