We are facing a problem programming S10 via JTAG.
Example designs: DDR4 and PCIe AvalonST.
18950 Device has stopped receiving configuration data.
18948 Error message received from device: Device is in configuration state.
209012 Opreation failed.
What should we check?
SVID mode: PMBus master
Clock source: Internal Oscillator
All voltages are in range and stable.
There is a known issue which user will have this error message when PCIe and DDR is used in the design. Can you please check if reference clock is supplied appropriately to this IP?
May i know what is the configuration scheme that you are using? Also, can i have wider view on the schematic? The connection between JTAG 10 header with FPGA?
This is weird. Can you ensure that the reference clock is supplying the clock frequency correctly to your PCIe and DDR? Also, can you try to change the TCK frequency to 6MHz? If it is not working either, try to use another piece of USB Blaster?
The problems were:
- No OSC_CLK_1 was provided.
- VccINT sense is being connected to 4th channel of Power manager (LTC2977). Swapping sence lines with Channel 0 by wires has almost solved the problem. All tests designs were loaded to Stratix and work fine.
But the rest of the problem is wires. It is impossible to hand boards to customer with wires around the board. Quartus has no means to select PM Channel other than default 0.
Is it possible to swap default PM channel by some constraints?
Which PM channel are you referring to? Are you saying the PMBus 0 and etc? If it so, it can be changed, however with limited selection. You can do that in Quartus.
Meanwhile for the wiring part, it is not recommended to do so due to robustness of the board. However, you will need to check with the customer and see whether they accept it or not.