Stratix 10 performance

[Vladimir_Y_Intel]

Hi,

It's been some time we are working with Stratix 10 device. There is a design that we can't close timing on Stratix.

After comparing this design on other options (Virtex 7, Ultrascale+),

it seems that that Stratix 10 performance on this design is around Virtex 7, which is surprising. Ultrascale+ device is surpassing Stratix 10.

Is it something expected? Did anybody see better results? What switches should we pay attention to?

Thanks,

Vladimir.

[sstrell]

Without knowing the design or what you've tried so far, it's hard to tell. If you're not familiar with the Hyperflex architecture (such as the fact that you shouldn't use asynchronous clears), check out online trainings about it, starting here:

https://www.intel.com/content/www/us/en/programmable/support/training/course/os10ihypret.html