Hi!!!!Is it possible to implement asynchronous RAM in Stratix II™ devices? If it is possible, how can I do? I need your help... is very important for me because ,I'm working with this device in my final career proyect... Thx for your help!!! Mary
No. Note that asynchronous RAM are almost never necessary. For example, the addressing is eventually being fed by a register, so it's just a matter of absorbing that into the RAM. Quartus Integrated Synthesis can do a pretty good job of that. But looking at a common example:Designer has a counter that is used to drive the address of a register. Because the counter is a feedback structure(it's input for next state is dependent on its output of current state), those registers seemingly can't get absorbed into the synchronous memory. But you can just code it where the synchronous memory gets the same logic as the counter's feedback, i.e.: counter <= counter + 1; address <= counter + 1; So now the address can be absorbed into the memory, since it has the same value as the counter at all times, but it does not have a feedback loop on itself.
At this moment I am implementing a processor that works with memory cache. And I'm driving three different clocks. It is complicated to try to synchronize the RAM memory with them. For this reason I am looking for information on how to implement an asynchronous memory to simulate as cache.
Making the RAM out of FFs will allow for an asynchronous read, but will be large and slow. Probably the best thing I can think of is to have 3 RAMs, all written by the same clock(I assume you just mean asynchronous reads), and read by the 3 clocks.
I need to work with embedded memory. Also, the 3 clocks are to handle the processor, memory management unit and main memory that will be outsourced. The three clocks are totally independent.I have a big problem, no?
How big is the cache? I think doing it in triplicate is the easiest method, assuming there's enough memory. If you need more, then you need to develop some interface. (Note that you already had difficulties if asynchronous RAMs were available. No RAMs have 3 read ports, so you would need arbitration logic that handles who is reading the memory, and that arbitration logic needs to work across independent clock domains, which means handshaking or some other cross-domain logic.) So I don't think asynchronous memory was going to be very easy either.Being synchronous, you can do reads from two of the domains(since you can have two synchronous read ports), and the third domain would need to have its read requests go through a DCFIFO into one of the existing two domains, and then the read data go back through a DCFIFO. And of course thinking about it, you wouldn't need three copies of your RAM for the more trivial solution, you would need 2. I assume you also disable all reads while doing writes, or have some way of ensuring you're writing to a location not being read on another clock domain?
The largest SII has 9 M-RAM blocks(512K bits, so you would make them 256Kx2 for your Main memory). So that's not even half of your main memory. If you start stitching M4Ks together, you need 64 of them stacked deep to do a single 256Kx1, so using every one you'll get another 11-12 bits, but you just don't have enough for the main memory.If the main memory is off-chip, then the cache should fit into M512s pretty easily, and if you aren't using them all, then doubling them is pretty straightforward(I don't know what size device you're targeting)