Stratix II EP2S90F1020 JTAG issue

[tony_yu]

Dear Intel Employee,

I have a Stratix II EP2S90F1020 FPGA. I just want to verify the IDCODE and do the boundary scan before configuration. I wired all 8 bank VCCIO (3.3V), VCCPD (3.3V) and VCCINT (1.2V) to the power supply, then connect all JTAG pins (TDI, TMS, TCK, TDO) to my JTAG. When I run the JTAG chain, it always failed. Is there any tricky step up for this specific chip to run JTAG without configuration?

I have tried two vender's JTAG ( XJTAG and JTAG Lives), both of them not work.

Sincerely, 

[JohnT_Intel]

Hi,

Could you check the nStatus to see if it is high to indicate that the FPGA is ready? May I know what is the issue that you are facing on the JTAG? Do you have another board to test it out?

[tony_yu]

Hello, 

Thanks for your quick response. Now we are testing the single FPGA chip for our customer, we use jumper wire to connect all the required pins through socket, then power up all power pins (VCCINT, VCCIO, VCCPD)  by a power supply instrument and connect all JTAG pins (TCK, TMS, TDI, TDO) to the XJTAG. In the JTAG software, we could not get any return data from TDO. I checked nSTATUS, it was low. Is that means the FPGA is not ready? So how can we let it ready? are there any additional setup?

Best,

[JohnT_Intel]

Hi,

If the FPGA is power up correctly then we should be expecting that the nStatus is high.

Could you help to check if the power supply is correctly powered, nCE is low, and nConfig is high?