Stratix IV GX 230 DDR2 Example Design Issue (EP4SGX230KF40C2)

[joseph_wu]

Hi all,

I was trying to use the DDR2 controller with UniPHY IP with the following steps,

1. Set the parameters for the memory controller (as attached)
   1. According to the datasheet of the DDR2 provided (Samsung D2SS28081XH25AA DDR2-800)
2. Generate example design
3. Perform Analysis and Synthesis
   1.  Also specified the correct device name before Analysis and Synthesis
4. Run tcl script for pin assignment
   1. ddr2_pin_assignments.tcl (generated automatically)
5. Run tcl script for pin location assignment (as attached)
   1. Generated according to user manual
6. Do a full compilation
7. Program the FPGA with .sof generated

The problem is on-board test (step 7), and it seems the result signals are wrong

1. LEDs for test complete
   1. complete: high
   2. pass: low
   3. fail: high
2. LEDs for calibration signals
   1. done: low
   2. success: low
   3. fail high

Have been stuck with the issue for weeks and couldn't find a solution.

Could someone please give some advices.

Thanks in advance!

Joseph

[AdzimZM_Intel]

Hi Joseph,

May I know which Quartus version and your machine environment that you used?

Can you shared the example design with me?

Thanks,

Adzim

[joseph_wu]

Hi Adzim,

My Quartus version: Quartus Prime 18.1 Standard Edition

Do you mean my laptop environment by machine environment?

The attached is the example design.

Thank you!

Joseph

[AdzimZM_Intel]

Hi Joseph,

Thanks for sharing the design file.

Have you tried to simulate this example design?

But I think that the issue is related to the hardware.

• Can you check the clock frequency on the board?
• Make sure all connections are right.
• If possible, can you test with different memory and other Stratix IV board?

Thanks,

Adzim

[joseph_wu]

Hi Adzim,

Yes, I have tried simulating the design and the waveform seems normal.

As for the hardware,

• I have tried programming the FPGA with 400 MHz (highest acceptable frequency for DDR2) and 300 MHz, but both failed
• Could you please provide the connection references for the example design for me to check?
• I could not test with different memory and other Stratix IV board for now

Thank you!

Joseph

[Terasic-Dav]

Hi Joseph,

I was told you've been using our DE4-230, including the implementation of this DDR2 example design. 

After reading through your steps, the first thing I'd check is whether the pin assignment is correct. The other possible cause is whether the parameters defined in the example design meet the criteria of the board and the spec. of DDR2 SO-DIMM used. 

It would be a lot easier if you could refer to our DDR2 demo code from section 5.5 DDR2 SDRAM in our DE4 user manual where you get to test the entire the DDR2 SO-DIMM. This can help you confirm the hardware is in perfect condition. 

Cheers,

David

[joseph_wu]

Hi David,

Thanks for responding.

I referred to your DDR2 demo code's pin planner for the pin assignment, it should be right.

As for the parameters, I really couldn't find a recommended or formal setting for DE4-230. I tried the parameters setting for your DDR2 demo code according to QSYS file but still couldn't solve the issue. Could you please offer a recommended parameters setting?

I also tried the DDR2 demo code but got the error when executing the demo batch file “test.bat” under the batch file folder DE4_DDR2\demo_batch\dim1 as attached.

Could you please provide some advices?

Thank you!

Joseph

[AdzimZM_Intel]

Hello Joseph,

I'm sorry for the delay on this topic.

May I know any update on this?

Thanks,

Adzim

[AdzimZM_Intel]

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