Stratix IV XAUI Transceiver Lanes

[Altera_Forum]

I have a question about using a Stratix IV MGT for XAUI going to a 10 GbE PHY chip. Basically, in order to simplify routing, the lanes between the FPGA and PHY are scrambled, not in an order of MSB to LSB or vice versa. Therefore, I get errors as shown below during compilation. 

 Error (167038): Channel 0 transceiver atom "XAUI_TX[0]" cannot be placed on the transceiver block channel 2 at location PIN_T4 Error (167038): Channel 1 transceiver atom "XAUI_TX[1]" cannot be placed on the transceiver block channel 3 at location PIN_P4 Error (167038): Channel 2 transceiver atom "XAUI_TX[2]" cannot be placed on the transceiver block channel 1 at location PIN_AB4 Error (167038): Channel 3 transceiver atom "XAUI_TX[3]" cannot be placed on the transceiver block channel 0 at location PIN_AD4 Error (167038): Channel 0 transceiver atom "XAUI_RX[0]" cannot be placed on the transceiver block channel 2 at location PIN_U2 Error (167038): Channel 1 transceiver atom "XAUI_RX[1]" cannot be placed on the transceiver block channel 3 at location PIN_R2 Error (167038): Channel 2 transceiver atom "XAUI_RX[2]" cannot be placed on the transceiver block channel 1 at location PIN_AC2 Error (167038): Channel 3 transceiver atom "XAUI_RX[3]" cannot be placed on the transceiver block channel 0 at location PIN_AE2    I have to assign pins like Quartus wants in order to get my design to compile. My question is, is there a way to take out these scrambled connections in the FPGA fabric? I am using the Altera XAUI PHY core. I have read through the documentation but haven't found a solution yet.    Thanks, Mark

[Altera_Forum]

I believe if you want to use the hard xaui IP, you don't have the choice of changing the channels around. I think the soft IP version of the core will let you assign arbitrary channels.