Stratix V, HSSI transceiver I/O pins, is configuration required prior to JTAG testing

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Stratix V, HSSI transceiver I/O pins, is configuration required prior to JTAG testing

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Solution ID: rd09132010_18 notes that for the ARRIA II GX,

"Prior to attempting to perform IEEE 1149.6 JTAG testing on transciever pins, you must first configure the device with a valid bitstream. JTAG boundary scan support for transceivers must use post-configuration BSDL files."

Does this configuration requirement apply to the Stratix V HSSI pins?

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