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SubLVDS support details on Max10

Lumin_Zhang
Employee
235 Views

HI, I have a couple questions regarding to the SubLVDS (1.8V) on Max10.

1. is there any addtional speed limitation if Max10 is using subLVDS? Can we expect the same speed level as 2.5V LVDS interface?

2. In the max10 LVDS application note, it was mentioned that SubLVDS still use 2.5 Input buffer. Does it mean I need to set VCCIO to 2.5V for subLVDS receiver bank? fig17 in page28 in ug_m10_lvds.pdf shows this however this is conflicting with Table25 in page24 in Max10 device datasheet to have subLVDS VCCIO set at 1.8V. If I'm going to implement both subLVDS TX and RX pairs in the same Max10 device, does it mean I need to separate the TX and RX pair in different bank with different VCCIO?

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2 Replies
EngWei_O_Intel
Employee
214 Views

Hi Lumin

Referring to Table 4 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf

For Sub-LVDS IO standard as Input (receiver), it needs 2.5V Vccio, wheareas it needs 1.8V Vccio for Sub-LVDS output (transmitter).

It is also mentioned in Table 3 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf

Thanks.

Eng Wei

EngWei_O_Intel
Employee
149 Views

Hi Lumin

I understand that you are currently communicate with Intel technical team for this thread.

With that, I will close the thread and transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Eng Wei

 

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