System ID and Time Stamp Not Found

[Altera_Forum]

I have developed a hardware design with Nios II processor. I am using a cpu, a sys clk timer, an interval timer, jtag uart, system id, sdram and pios. I am using the DE0 board. I have used both Quartus 11.1 sp2 and 12.0. I try to run the basic 'Hello World' program. Everything worked well for sometime. However, after that when I try to load the C program into the FPGA and Run (Run As -> Nios II Hardware), without any reason I get an error,  

"Error: Connected system ID hash not found on target at expected base address". However after sometime the code runs once again for sometime until I get the same error. If I click System ID Properties I get:  connected system id: not found connected system timestamp: not found  This is a very strange problem since the same code works sometimes but during other times it does not work.   The same design works well without the SDRAM component. However, the existing problem began only when I included the SDRAM in the system. I am also using a button to reset the processor.  What could be the problem here? Any suggestions would be much appreciated

[Altera_Forum]

Hi migara8, 

 Whenever I've come across this, it's been because the JTAG UART is unable to communicate with the system for some reason. For me, it's typically been that some reset being asserted somewhere. If the SDRAM is interfering, it may be that it is holding bus access, preventing the UART from accessing the system ID.  It would help if you can post your Qsys system but you can also try to track it by using SignalTap to monitor the bus.  Scott

[Altera_Forum]

Hi Scott, 

Thank you for your suggestion. A you say I also think that there is some reset being asserted somewhere. Attached here is my Qsys design for your reference. I am using the DE0 board. What can I do about this problem? I really appreciate your help and suggestions.

[Altera_Forum]

Hi migara8, 

 Would it be possible to attach your qsys file instead? The HDL instantiation hides the connections which is the only way to see what might be going on. Is there an example design for the DE0 board you can compare against?  Scott

[Altera_Forum]

Hi Scott, 

Here is the qsys design. I am quite confused about the problem. I really appreciate your help.

[Altera_Forum]

Let me preface this by saying I'm no Qsys expert. 

 It looks like your processor is trying to run from the SDRAM. Was it previously running from the on-chip memory and can you run it from there while still including the SDRAM in your system? I would recommend using signaltap to see what the bus is doing, especially in regard to the SDRAM S1 signals. I'm guessing the SDRAM might be holding the bus via its wait request but can't be sure.  It also looks like you removed the system ID component but I think it's an indication of a bigger problem. If you add it back, you can try triggering on the system ID address when trying to access it through Eclipse. Whether it's the SDRAM or not, something is interfering with bus communications.