SystemC an alternative to Verilog??

[Altera_Forum]

Hello, quick question for everyone. Are there any plans by Altera to permit SystemC in Quartus? I've been reading a lot of the benefits of SystemC and would like to try it out. Is SystemC an alternative to Verilog? 

 Thanks, joe

[Altera_Forum]

If you've been reading a lot about SystemC then you may have noticed that the focus of this language (if you call it a language at all) is high level simulation and verification. Synthesis also can be done with it but at the cost of some overhead compared to Verilog and VHDL. Because of that, I assume that FPGA vendors will not adopt SystemC. To my knowledge, Mentor ModelSim does support SystemC and Verilog/VHDL co-simulation.

[Altera_Forum]

I believe SystemVerilog is becoming the next mainstream language since it allows usage of the existing Verilog constructs and provides constraint-random testing.

[Altera_Forum]

I belive you are right , Systemverilog is a powerful language. I am fairly new to this business, but I have been using both SystemC and SystemVerilog and as I see it, there is no need for SystemC since Systemverilog offers a high level of abstraction and is well suited for simulation and verification. (And even synthesizeable :)). 

 But as i said, I am fairly new to this and I would appreciate inputs on my opinion.   However, altera need to pick up the pace finish the quartus support for systemveilog.

[Altera_Forum]

systemverilog might be of high level abstraction, but systemc offers early software verification, where the system designers and software engineers can both use the same platform based hardware ip models. 

systemC has a great scope to grow. Like, it has an advantage for software and hardware engineers to have a single common language. But this has many business issues, like the hardware ip vendors will have a much loss as their existing ips have their identities with vhdl or verilog.