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TSE MAC phy MDIO write not working.

JDeff
Beginner
257 Views

I am able to read register 0 of my phy by initiating a read command to address xA0 in the Avalon bus. the result is x1140. However if I try to write to this same address, no MDIO transaction takes place and the waitrequest remains high indefinitely. a reset of the MAC avalon port is required to regain access. Am I missing a step to get the write transaction to complete?

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4 Replies
Deshi_Intel
Moderator
234 Views

Hi,

 

I noticed you are accessing mdio space 1 address 0xA0 instead of address 0x080 is due to you are using the address space for PCS function already ?

 

Some of the factor that I think maybe affecting your mdio write access is like below

  1. TSE IP MDIO host clock divisor setting - ensure MDC clock frequency does not exceed 2.5MHz
  2. External PHY Initialization using MDIO address -> TSE MAC Base Configuration Reg 
  • 0x0f for mdio_addr0
    • 0x10 for mdio_addr1
    • have you initialize and configure mdio_addr1 to correct PHY chip address before you perform wrire/read access ?
  1. Did you connect MIDO output enable connection for "mdio_oen" port, correctly ?

 

Thanks.

 

Regards,

dlim  

JDeff
Beginner
234 Views

Hi Dlim,

 

My core instantiation includes the PCS. My understanding is address space 0 is unavailable when using the PCS function.

  • My Avalon clk is 100 mhz, and the divider is set to 80, so i should have an MDC of 1.25MHz
  • I write x"0F" to addresss x"10" before initiating a read or write to address x"A0". My phy address is "1111"
  • Again, I am able to read data from the phy, but a write locks up the avalon interface with waitrequest held high and no transaction initiated on the MDIO bus
  • I have MDIO connected as below :

MDIO  <= mdio_out when mdio_oen = '0' else 'Z';

  •  
Deshi_Intel
Moderator
234 Views

Hi,

 

Yup, address space 0 will be occupied when PCS function is in used as explained by the TSE user guide doc.

 

Your MDIO setup looks correct.

 

I presume you have supply <= 125Mhz clock correctly to MAC control register clk pin as well. (which is the avalon bus clock)

 

My other debug suggestion for you is

  • Have you tried to run TSE simulation before to ensure your whole Quartus design is connected and working correctly. Then you can cross check your MDIO in sim waveform as well. This is to ensure nothing wrong with your Quartus design
  • Have you tried to access other reg address of your external PHY chip besides 0xA0 ?
  • Lastly, you can also use Oscilloscope to probe your on board external PHY chip MDIO bus when you try to perform a write transaction.
    • If no signal toggling on board then you know FPGA TSE IP doesn't send out the MDIO write transaction
    • Else if you saw signal toggling on board then maybe there is an issue with your external PHY chip

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
232 Views

HI,


I have not hear back from you for close to 1 month.


Hopefully you are making progress on the debug.


For now, I am setting this case to closure. Feel free to post new forum thread in future if you still have enquiry in future.


Thanks.


Regards,

dlim


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