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The Fitter cannot place 3 periphery component(s) (1 HSSI_PLD_INTERFACE(s), 2 HSSI_PMA_TX_BUF(s))

Visshnu
Beginner
492 Views

Hi,

In my design ,I have native phy 10g  transceiver which works in duplex mode .when compiled ,it ends up in this error during fitter

Error(14566): The Fitter cannot place 3 periphery component(s) due to conflicts with existing constraints (1 HSSI_PLD_INTERFACE(s), 2 HSSI_PMA_TX_BUF(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 HSSI_PMA_TX_BUF, which is within Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP trcvr_10g_altera_xcvr_native_a10_180_xx77c5q.
Error(16234): No legal location could be found out of 12 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between the HSSI_PMA_TX_BUF and destination HSSI_RX_PCS_PMA_INTERFACE
Error(175022): The HSSI_PMA_TX_BUF could not be placed in any location to satisfy its connectivity requirements
Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)
Error(175001): The Fitter cannot place 1 HSSI_PMA_TX_BUF, which is within Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP trcvr_10g_altera_xcvr_native_a10_180_xx77c5q.
Error(16234): No legal location could be found out of 12 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between the HSSI_PMA_TX_BUF and destination HSSI_RX_PCS_PMA_INTERFACE
Error(175022): The HSSI_PMA_TX_BUF could not be placed in any location to satisfy its connectivity requirements
Error(20196): Location(s) already occupied and the components cannot be merged. (2 locations affected)
Error(175001): The Fitter cannot place 1 HSSI_PLD_INTERFACE.
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175007): Could not find uncongested path between the HSSI_PLD_INTERFACE and destination HSSI_DUPLEX_CHANNEL_CLUSTER
Error(175022): The HSSI_PLD_INTERFACE could not be placed in any location to satisfy its connectivity requirements
Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error(16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 17 errors, 2 warnings

I have two  modules which are port mapped  to transceiver 10g,one for rx and another for tx  .I am using cyclone 10gx development board . Is there a workaround for my case or should I use rx and tx separately ?

0 Kudos
4 Replies
Deshi_Intel
Moderator
482 Views

Hi,


I am confused. Are you using duplex or simplex mode ?

  • You mentioned you used duplex mode but then there is Tx and Rx module design ?


Can you share your Quartus design QAR file then I can help you to review your fitter error better ?


Thanks.


Regards,

Deshi


Deshi_Intel
Moderator
455 Views

Attached is fitter error explanation

 

Deshi_Intel
Moderator
452 Views

Additional feedback to you.


Don't mix up duplex and simplex setting in one design else you may face functionality error later

  • Right now your design both MAC and PHY IP setting is set to duplex mode but in RTL connection, you force split it into simplex connection
  • If you want to create simplex design then pls ensure MAC and PHY IP are set to simplex mode where you should have
    • one set of MAC + PHY Tx IP design and its connection
    • another set of MAC + PHY Rx IP design and its connection


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
410 Views

HI,


I hope I have clarified on the design implementation expectation for duplex and simples design


For now, I am setting this case to closure.


Thanks.


Regards,

dlim


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