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The Fitter failed to find a legal placement for IOPLL with DIB of Stratix 10.

OrF
Employee
527 Views

I got the next Error from the Fitter while trying to synthesis with DIB 

The Fitter Failed to find legal placement for my IOPLL 

is there a way to find out which PLL is preferred by the DIB , or vise versa  any methodical way    to find out which DIB subsystem / channel or  bank  I  choose - since I know what are my free PLL.

(BTW I have many free pll, but somehow they does not good enough for usage by the fitter due to DIB location )

this is the Error I get:

Error (14996): The Fitter failed to find a legal placement for all periphery components
Error (14986): After placing as many components as possible, the following errors remain:
Error (175001): The Fitter cannot place 1 IOPLL.
Info (14596): Information about the failing component(s):
Info (175028): The IOPLL name(s): f1|cnvr_dib_rx_pll_inst|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll
Error (16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): There is no routing connectivity between source DIB_DIB_PHY and the IOPLL
Info (175026): Source: DIB_DIB_PHY f1|cnvr_dib_wrapper_ins|dib_rx_2_22|dib_0|dib_ch|arch_inst|phy_inst|xphy_inst
Info (175013): The DIB_DIB_PHY is constrained to the region (442, 290) to (442, 290) due to related logic
Info (175015): The I/O pad DIE1_dib_pad_2_22_0[0] is constrained to the location PIN_DIB0_CH22_X1Y2 due to: User Location Constraints (PIN_DIB0_CH22_X1Y2)
Info (14709): The constrained I/O pad contains this DIB_DIB_PHY
Info (175015): The I/O pad DIE1_dib_pad_2_22_3[22] is constrained to the location PIN_DIB94_CH22_X1Y2 due to: User Location Constraints (PIN_DIB94_CH22_X1Y2)
Info (14709): The constrained I/O pad drives a DIB_DIB_IO_WRP, which drives this DIB_DIB_PHY
Info (175021): The DIB_DIB_PHY was placed in location DIBDIBPHY_X442_Y290_N1
Error (175022): The IOPLL could not be placed in any location to satisfy its connectivity requirements

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11 Replies
AqidAyman_Intel
Employee
483 Views

Hello,


Thank you for reaching out Intel FPGA Community.


This error basically caused by the Fitter cannot place the specified logic element in the design.

Could you share the test case design with us? so that I can try to replicate and isolate the issue.

You can choose to share here or privately.


Just let me know which you prefer.


Regards,

Aqid


OrF
Employee
478 Views

I prefer to share the data base privately , to where can I upload it ? (inside intel right ? ) what is the  file  (QAR, Quartos Archive file )?  

Thanks

Or. 

AqidAyman_Intel
Employee
425 Views

Hi Or,


I have initiated an email for you. You can share the .qar file through that. Kindly check your inbox.


Regards,

Aqid


OrF
Employee
389 Views

Hi I answered in the email , but didn't get any reply so I post here as well..

the QAR file is very big , and since I'm Intel employee  can you share a place I can upload the QAR file ? 

Thanks

Or. 

 

AqidAyman_Intel
Employee
378 Views

Hi Or,


I have replied through email. Can you see it now?


Regards,

Aqid


OrF
Employee
364 Views

got your mail , and put the path to qar file .

reply to email (Intel Customer Support <supportreplies@intel.com>)

Or. 

AqidAyman_Intel
Employee
360 Views

As for now, I am not getting your reply yet.


OrF
Employee
353 Views

I sent 2 times to the support did you get it eventually ? 

AqidAyman_Intel
Employee
336 Views

Okay got it. I managed to reproduce the error from my side. I will start with debugging and communicate back with you if I have any findings.


AqidAyman_Intel
Employee
26 Views

Hi Or,


Apologies for the delay. I have several tasks and make me overlook for this. I am still trying to fix the error.


Can you follow this guideline as below link and see if the error still remains?

https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/clocking-options.html


Regards,

Aqid


OrF
Employee
15 Views

Hi Aqid

I don't see any relation to my issue with the suggested guideline.

1.  in the document you send , it is about clock/pll which "Feeds" the DIB, in my case the the PLL is Feed by a clock which transfer from the other die via the DIB "Source-synchronous" architecture, the the clock which arrives from the DIB is feeding the PLL ... 

2. more over , if  I would like learn from the document you sent  , it does not say anything how to choose specific pll. which might solve the Fitter issues.

 

if you can please elaborate what did you mean , that I should follow this guideline in my design , since I don't find any relation to my issue, or something I can do.

 

Thanks

Or.  

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