The IO Standard and Pin Configuration

[Altera_Forum]

Dear all: 

  I have some question about the IO standard when doing my design. Could you please help me to resolve that?    I use EP3C40F780 as my main processor. And I want to use EPCS serials device as the configuration device. I want to configure the IO Bank1 as LVDS and the VCCIO pin was connected to 2.5V, but the configuration pin "nCSO" was still in this bank. So I was confused that if this bank was powered by 2.5V, are there any problems when configuring the device?    Another question is that must the CLK0 and CLK1 pin meet the LVDS standard when the bank was powerd by 2.5V. Can these tow pins receive LVTTL clock signals?    Thanks a lot!   Shanwu

[Altera_Forum]

Powering the nCSO pin at 2.5V should not be a problem. The datasheet for EPCS devices indicate that Vih is 0.6*Vcc so even at 3.3V you only need 2.0 V for a logic high. BTW, you can use 3rd party flash devices in place of the EPCS device and some of these do run at 2.5V. 

 With regards to the clock; if you are powering the bank at 2.5V, you should provide a 2.5V single-ended clock rather than 3.3V. However, if you are using the clock to drive LVDS transmitters or receivers, you may have to use a differential clock input. I'm not sure about Cyclone III but this was necessary on Stratix IV.  Jake