The Jtag pins of the EPM7128s Cpld (MAX7000) can be used as IOs?

[Altera_Forum]

Hi, I'm doing a little project with an old Max 7000 EPM7128S Cpld. I'm already using all normal IOs, but I need four more. Seems that the Jtag pins can be used as IOs.  

Is it true? If so, how the Cpld knows when to use the Jtag pins or the IOs? By the voltage?  And about the GLCK1, GLCK2. GCLR and OE1 pins? These are listed also has Input, but I cannot use it as a general purpose IO? In recent cplds we can use this pins as generic IOs.   The datasheet is here:  https://www.altera.com/en_us/pdfs/literature/ds/archives/m7000.pdf  thanks

[Altera_Forum]

Hi, 

yes, the JTAG pins of the mentioned device can be used as general I/O pins. The selection of JTAG or general I/O is written into a device programming file. Dedicated clock (GCLK) and output enable (OE) pins can be used as general input but not output pins.  Regards, Martin

[Altera_Forum]

Isn't it so that disabling JTAG pins prevents further JTAG programmer access to the device?

[Altera_Forum]

Hi, 

yes, after programming of a project with the JTAG disabled is further JTAG programing no longer possible. But there is another non-JTAG programming method that can cope with the JTAG disable option but it is necessary to use a device programmer such as Altera Programming Unit APU or the 3rd party programmers from BPM, Data IO, Elnec or System General.  Regards, Martin

[Altera_Forum]

Thanks... But I don't want to disable the jtag pins.  

So I can use GLCK1, GLCK2, GCLR and OE1 pins for general input then? How the chip knows then if the GCLR, for example, is a general input or a clear? In the recent MAXII for example there is an option for the chip to specify if these pins are general IOs or these specific functions. But for Max7000 there is no such option.