The configuration voltage problem in Cyclone IV GX FPGA

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

The configuration voltage problem in Cyclone IV GX FPGA

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According to your documents 'Cyclone IV Device Handbook' Page 175:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12901&stc=1

The High logic of the nSTATUS, CONF_DONE, nCONFIG, MSEL[] should be the VCCIO of bank3.

Meanwhile, according to your documents '150-0311003-B1 6XX-43286R'; it is your model design 'cyclone iv gx fpga development kit board'. In your design schematic file, the bank3 has a 1.8V support voltage, but the nSTATUS, CONF_DONE, nCONFIG, MSEL[] configuration pins in bank3 are linked to a 2.5V high logic.

So, it that ok for us to have a 1.8V Bank3 support while link the nSTATUS, CONF_DONE, nCONFIG, MSEL[] to 2.5V high voltage?

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