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The future for AHDL

raviganesh
Novice
363 Views

AHDL is wonderful language. I have worked on 4 HDL languages, ABEL, AHDL, Verilog and currenlty SpinalHdl.

Here is my recent work with SpinalHdl 

 

On some aspects like an array of modules, AHDL outshines SpinalHdl. AHDL a 20 year old language continues to rock.

 

What can Intel do with AHDL:

1. Amalgamate AHDL and block definition and make a language called VisualAHDL

2. VisualAHDL shall generate Verilog - just like SpinalHdl

3. It shall take the best offerings from SpinalHdl/Chisel. Avoid the deep software complexities of Object Oriented Programming.

3. VisualAHDL shall be the most convenient RTL to work with. To make the long story short - it give  the same convenience as a WYSWYG editor. In 2 years from now only the most unfortunate will still be coding in Verilog.

4. What more: Xylinx users will use VisualAHDL for code entry!!

 

This requires some passionate visionaries in Intel. 

Is Intel thinking?

Ravi Ganesh

 

0 Kudos
13 Replies
raviganesh
Novice
339 Views

Unfortunately there is no BIll Gates in the hardware community. Charles Papon invented SpinalHdl and won the award for the best RiscV implementation in the world, because he used this tool. Inventions for more convenient HDL coding is coming from startups and Whizkids. The encumberments are a burnt-out lot with no passion for their work. Is it not astonishing that one individual created VexRiscV while a hundred engineers could not keep Nios alive.

 

SyafieqS
Moderator
328 Views

Ravi,


May I know what is your question?


raviganesh
Novice
299 Views

Thankyou for not deleting this post as irrelevant.

My question is When is VisualAHDL coming?

Well this is a question to Bill Gates/Steve Jobs in Intel if there is one

 

ak6dn
Valued Contributor III
320 Views

Is this you 11 years ago pushing AHDL?

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Can-you-simulate-AHDL-with-Modelsim/td-p...

Give it up, my man. AHDL is dead. Has been for quite a while. There is no business case for Intel doing anything with AHDL.

Verilog/SystemVerilog or VHDL for a close-to-hardware design methodology is now mainstream.

Higher level abstraction like OpenCL has much more of a following than any low level AHDL-like derivatives.

I have used Verilog since the late 80s and have found it to have the right balance between direct hardware description and higher level abstraction for behavioral simulation tasks, like test benches. It is descriptive without being too verbose.

I find VHDL to be needlessly verbose for my taste. Verilog is like programming in C, whereas VHDL is like programming in Pascal.

Either one gets the job done, but it just takes more (needless) typing to get it done in VHDL vs Verilog, in my opinion, for little benefit.

I sure others will disagree.

My 2c.

raviganesh
Novice
301 Views

Hi Donald,

I immensely appreciate your response and I feel very honored about your reference to my 11 year old post.

Here is my comparison of the verbosities:

Verilog:      assign Data = nCE? 16'hffff : 16'h0);
SpinalHdl: Data.setAllTo (nCE)
AHDL:         Data[] = nCE

Isn't AHDL short and sweet.

I will come up with another example using an array of modules. Verilog sucks. SpinalHdl pant's. AHDL shines.

I disagree AHDL is only for low level. Its state machines are as as good as SpinalHdl and far better than Verilog. It has tables and there is no equivalent in Verilog or SpinalHdl. And for connection of IP catalog components, AHDL is second only to block editor  And above all Intel's support for AHDL in Quartus is... I have nothing to complain.

 

Just imagine combining this brevity with a live graphical WYSWYG editor. And the final output will be Verilog. And when the engineer looks a the generated code, he will jump for joy and cry - Hey VisualAHDL where were you all these days?

 

I see a small window of opportunity. Before SpinalHdl or Chisel or some other Python Verilog generators dominate main stream HDL design entry, Intel has an opportunity to over take these new languages with a brand new paradigm for design entry - VisualAHDL.

 

A note on High Level Synthesis. I tired it a year back (my posts in this forum are the evidence)  and gave it up. It is like an auto router for PCB!!

And if openCL is great why no one designed a RiscV in OpenCL and bagged the first prize?

I strongly believe low level design entry is there to stay. 

 

Ravi Ganesh

 

ak6dn
Valued Contributor III
291 Views

No Verilog coder would write it like that. It would more likely be:

 

 

wire [15:0] data = {16{nCE}};

 

 

But that example is way too contrived. How about a simple 8b counter module with an async low reset:

 

 

module count (input wire clk, input wire rst, output reg [7:0] cnt);

always @(posedge clk or negedge rst)
    if (!rst)
        cnt <= 0;
    else
        cnt <= cnt+1;

endmodule

 

 

But the real point is AHDL is dead and is going nowhere. Only Altera ever used it, and they basically killed it years ago. RIP.

 

As to OpenCL, you may not like it, but it opens up FPGA design to non-hardware engineers. Sure programming in assembly language (ie, AHDL) is fun and efficient in terms of gates. But it is very inefficient in terms of time and manpower requirements.  For the same reason compilers and high level languages are the standard methodology in software development, and not programming in assembly language, as it is much more efficient in terms of manpower and productivity.

raviganesh
Novice
284 Views

I am very pleased to offer the design in the two languages. But the final winner will be array of counter, which is coming next.

 

SpinalHDL

class count extends component() {
var cnt = out Reg(UInt(8 bits)) init(0)
cnt := cnt + 1
}

clk and !rst are implied. That is SpinalHDL philosophy of removing verbosity.

 

AHDL

SUBDESIGN count
(
	clk : Input;
	rst : Input;
	cnt[7..0] : Output;
)
VARAIBLE
	myCnt : LPM_COUNTER WITH (LPM_WIDTH=8, LPM_DIRECTION = "UP");

BEGIN
	myCnt.clock = clk;
	myCnt.aclr  = !rst;
	cnt[]	    = myCnt.q[];
END;

 

raviganesh
Novice
275 Views

Hi Donald, 

Here is my challenge. Now it is an array of 16 counters each with a synchronous reset.

 

This is the AHDL code:

SUBDESIGN counts
(
	clk 	   	 : Input;
	rst[15..0] 	 : Input;
	cnt[15..0][7..0] : Output;
)
VARAIBLE
	myCnt[15..0] : LPM_COUNTER WITH (LPM_WIDTH=8, LPM_DIRECTION = "UP");

BEGIN
	myCnt[].clock = clk;
	myCnt[].sclr  = rst[];
	cnt[][]	    = myCnt[].q[];
END;

 

SpinalHDL

class counters () extends Component {
    val rst = in  Bits (16 bits)
    val cnt = out Vec (Reg(UInt (8 bits)), 16)
    
    for (i <- 0 to 15) {
        when (rst(i)){
            cnt(i) := 0
        } otherwise {
            cnt(i) := cnt(i)+1
        }
    }
}

 

 

Do you want to reconsider your views on AHDL "it is very inefficient in terms of time and manpower requirements."

I do not code much in Verilog, but this is the Verilog code generated by SpinalHdl. I hope it can be a better and human readable. I await your comments.

// Generator : SpinalHDL v1.6.4    git head : 598c18959149eb18e5eee5b0aa3eef01ecaa41a1
// Component : counters

`timescale 1ns/1ps 

module counters (
  input      [15:0]   rst,
  output reg [7:0]    cnt_0,
  output reg [7:0]    cnt_1,
  output reg [7:0]    cnt_2,
  output reg [7:0]    cnt_3,
  output reg [7:0]    cnt_4,
  output reg [7:0]    cnt_5,
  output reg [7:0]    cnt_6,
  output reg [7:0]    cnt_7,
  output reg [7:0]    cnt_8,
  output reg [7:0]    cnt_9,
  output reg [7:0]    cnt_10,
  output reg [7:0]    cnt_11,
  output reg [7:0]    cnt_12,
  output reg [7:0]    cnt_13,
  output reg [7:0]    cnt_14,
  output reg [7:0]    cnt_15,
  input               clk,
  input               reset
);

  wire                N1_l20;
  wire                N1_l20_1;
  wire                N1_l20_2;
  wire                N1_l20_3;
  wire                N1_l20_4;
  wire                N1_l20_5;
  wire                N1_l20_6;
  wire                N1_l20_7;
  wire                N1_l20_8;
  wire                N1_l20_9;
  wire                N1_l20_10;
  wire                N1_l20_11;
  wire                N1_l20_12;
  wire                N1_l20_13;
  wire                N1_l20_14;
  wire                N1_l20_15;

  assign N1_l20 = rst[0];
  assign N1_l20_1 = rst[1];
  assign N1_l20_2 = rst[2];
  assign N1_l20_3 = rst[3];
  assign N1_l20_4 = rst[4];
  assign N1_l20_5 = rst[5];
  assign N1_l20_6 = rst[6];
  assign N1_l20_7 = rst[7];
  assign N1_l20_8 = rst[8];
  assign N1_l20_9 = rst[9];
  assign N1_l20_10 = rst[10];
  assign N1_l20_11 = rst[11];
  assign N1_l20_12 = rst[12];
  assign N1_l20_13 = rst[13];
  assign N1_l20_14 = rst[14];
  assign N1_l20_15 = rst[15];
  always @(posedge clk) begin
    if(N1_l20) begin
      cnt_0 <= 8'h0;
    end else begin
      cnt_0 <= (cnt_0 + 8'h01);
    end
    if(N1_l20_1) begin
      cnt_1 <= 8'h0;
    end else begin
      cnt_1 <= (cnt_1 + 8'h01);
    end
    if(N1_l20_2) begin
      cnt_2 <= 8'h0;
    end else begin
      cnt_2 <= (cnt_2 + 8'h01);
    end
    if(N1_l20_3) begin
      cnt_3 <= 8'h0;
    end else begin
      cnt_3 <= (cnt_3 + 8'h01);
    end
    if(N1_l20_4) begin
      cnt_4 <= 8'h0;
    end else begin
      cnt_4 <= (cnt_4 + 8'h01);
    end
    if(N1_l20_5) begin
      cnt_5 <= 8'h0;
    end else begin
      cnt_5 <= (cnt_5 + 8'h01);
    end
    if(N1_l20_6) begin
      cnt_6 <= 8'h0;
    end else begin
      cnt_6 <= (cnt_6 + 8'h01);
    end
    if(N1_l20_7) begin
      cnt_7 <= 8'h0;
    end else begin
      cnt_7 <= (cnt_7 + 8'h01);
    end
    if(N1_l20_8) begin
      cnt_8 <= 8'h0;
    end else begin
      cnt_8 <= (cnt_8 + 8'h01);
    end
    if(N1_l20_9) begin
      cnt_9 <= 8'h0;
    end else begin
      cnt_9 <= (cnt_9 + 8'h01);
    end
    if(N1_l20_10) begin
      cnt_10 <= 8'h0;
    end else begin
      cnt_10 <= (cnt_10 + 8'h01);
    end
    if(N1_l20_11) begin
      cnt_11 <= 8'h0;
    end else begin
      cnt_11 <= (cnt_11 + 8'h01);
    end
    if(N1_l20_12) begin
      cnt_12 <= 8'h0;
    end else begin
      cnt_12 <= (cnt_12 + 8'h01);
    end
    if(N1_l20_13) begin
      cnt_13 <= 8'h0;
    end else begin
      cnt_13 <= (cnt_13 + 8'h01);
    end
    if(N1_l20_14) begin
      cnt_14 <= 8'h0;
    end else begin
      cnt_14 <= (cnt_14 + 8'h01);
    end
    if(N1_l20_15) begin
      cnt_15 <= 8'h0;
    end else begin
      cnt_15 <= (cnt_15 + 8'h01);
    end
  end


endmodule

 

 

 

ak6dn
Valued Contributor III
262 Views

Well, to array a construct in systemverilog i would use the generate block construct, so ...

module count (input wire clk, input wire rst, output reg [15:0] cnt [7:0])
genvar i;
generate
    for (i = 0, i < 16; i++) begin
        always @(posedge clk)
            cnt[i] <= rst ? 0 : cnt[i]+1;
    end
endgenerate

 

So I am done here. You are beating the proverbial dead horse. AHDL is dead. It is not coming back. No one except you wants it.

raviganesh
Novice
254 Views

Donald,

Thanks for the code. That was nice and compact.

 

Ok we will finish it off as Ravi the last surviving AHDL user and Donald the only other person interested in AHDL in  the Intel Community.

Hope Intel continues to support AHDL in the future versions of Quartus as it has done so far. 

Just like Microsoft unfailingly supports BASIC.

Adieu,

Ravi Ganesh

 

SyafieqS
Moderator
231 Views

Hi Ravi,


Yes indeed, AHDL will not be supported in future Quartus build, and now the feature related to it is slowly been deprecated e.g. KDB below. 


https://www.intel.com/content/www/us/en/support/programmable/articles/000090820.html


I suggest you to go over Verilog/VHDL which is standard industry used. Let me know if there is any update. Thanks for the feedback 


SyafieqS
Moderator
212 Views

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


raviganesh
Novice
200 Views

Unfortunately this is not a simple question like "Device not configuring or pin not toggling" It is the future for AHDL - which is the founding language for Altera. Google has adopted Chisel and designing ASIC with it. In a few years many will follow suit. Nobody asked for Chisel. Some visionaries invented Chisel. It is sad that no one in Intel who wants to reinvent AHDL which is as good as of not better than SpinalHDL or Chisel as far as coding for RTL is concerned.

Sorry no kudos to anyone 

 

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