The interconnection between ADC and Cyclone10GX FPGA

[MinzhiWang]

Hello Guys, I have posted several threads to ask several questions about new FPGAs for us, which is Cyclone 10 GX FPGA.

The latest one is https://community.intel.com/t5/Programmable-Devices/How-to-route-XCVR-IO-from-Cyclone10GX-to-SFP/td-p/1561767?emcs_t=S2h8ZW1haWx8YWNjZXB0X2FzX3NvbHV0aW9uX3JlbWluZGVyfExSRVE2SEdIWVE3STdMfDE1NjE3ODR8T1RIRVJTfGhL 

Because I can't reply in Intel forum, I want to give my thanks to FvM, thank you very much.

I have to keep ask question with new post, now I have the question about the interconnection between ADC and FPGA. Our ADC is serial LVDS ADC. I remember I asked one question about FCO and DCO, and FvM give us the solution. Now the new question is how to connect FCO and DCO between ADC and FPGA. Do we need to assign dedicated clock pins for them? Or can we just assign normal LVDS differential pairs for them as the samping data output of the ADC? 

[AqidAyman_Intel]

May I know what is the application in your design for ADC interface in Cyclone 10GX?

[FvM]

Hi,
you need dedicated inputs for clocks driving a PLL, for SERDES reference clocks specifically a dedicated input in the same bank.

Clocks not driving a PLL must not necessarily use dedicated inputs, but achieve better performance (lower jitter and skew) if they do.

The actual answer depends on your ADC sync scheme and timing margin.

[AqidAyman_Intel]

Hi Minzhi,

May I know if you have any other questions regarding this?

Regards,

Aqid

[AqidAyman_Intel]

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