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Altera_Forum
Honored Contributor I
1,794 Views

The problem for using DPA PLL

Hi, 

 

for my project, I need receive 5 channels 500M LVDS sigal and with 50M sync following clock, 

I add a PLL for every following clock and generate 50M Phase342, 500M Phase180, 50M Phase288 Duty10 three clocks and connected to serdes. 

My FPGA is 5CGXFC7D6F27C7 own 7 PLLs. 

Besides these 5 PLL, i also use one for system clock which refclk input is osc. Totally 6 pll, and Place and Route can pass successfully. 

In order to improve sampling accuracy, i open the dynamic phase adjust (DPA) function for those 5 PLLs. 

When place and route, the error is shown below: 

 

Error (175020): Illegal constraint of fractional PLL to the region (x-coordinate, y- coordinate) to (x-coordinate, y-coordinate): no valid locations in regionError (175020): Illegal constraint of fractional PLL to the region (x-coordinate, y- coordinate) to (x-coordinate, y-coordinate): no valid locations in region 

 

is this means if i open DPA function of PLL, the FPGA cannot use 7 PLLs anymore? 

How can I solve this problem? 

Thanks in advance. 

 

Qi
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11 Replies
Altera_Forum
Honored Contributor I
184 Views

Insert an ALTCLKCTRL megafunction in the clock path between the dedicated clock input pin and the Altera_PLL. Note, using a global primitive or global signal assignment for the clock signal is not sufficient, the ALTCLKCTRL megafunction must be instantiated in your design. 

 

This is not necessary when the clock input pin has dedicated access to the Altera_PLL.
Altera_Forum
Honored Contributor I
184 Views

 

--- Quote Start ---  

Insert an ALTCLKCTRL megafunction in the clock path between the dedicated clock input pin and the Altera_PLL. Note, using a global primitive or global signal assignment for the clock signal is not sufficient, the ALTCLKCTRL megafunction must be instantiated in your design. 

 

This is not necessary when the clock input pin has dedicated access to the Altera_PLL. 

--- Quote End ---  

 

 

the PLL output will connect to non-DPA serdes, if i add one clkctrl between input and PLL, the quartus will show error message: 

 

pll which drives at least one non-DPA-mode SERDES, must be driven by a dedicated input
Altera_Forum
Honored Contributor I
184 Views

The issue is not related to the PLL outputs, but rather the input to the fractional PLL. When using fractional PLLs the input clock to the PLL should not be driven directly from the Clock pin. You should insert a Clock control block between the FPGA clock input pin and the PLL as shown below:https://alteraforum.com/forum/attachment.php?attachmentid=14487&stc=1  

 

Also check which PLL is the one affected. You may need to use the clock control for PLLs that do not connect to DPA blocks. for ones that connect to DPA, the PLL should be driven directly from the Clock input pin of the FPGA.
Altera_Forum
Honored Contributor I
184 Views

 

--- Quote Start ---  

The issue is not related to the PLL outputs, but rather the input to the fractional PLL. When using fractional PLLs the input clock to the PLL should not be driven directly from the Clock pin. You should insert a Clock control block between the FPGA clock input pin and the PLL as shown below:https://alteraforum.com/forum/attachment.php?attachmentid=14487&stc=1  

 

Also check which PLL is the one affected. You may need to use the clock control for PLLs that do not connect to DPA blocks. for ones that connect to DPA, the PLL should be driven directly from the Clock input pin of the FPGA. 

--- Quote End ---  

 

 

Thanks for support. actually now, i need five LVDS following clk input connected to the PLL with the DPA function. only the osc input one for system using do not need DPA function. 

Totally six pll, five of them with DPA function and one without DPA.
Altera_Forum
Honored Contributor I
184 Views

Use the clock control block on the PLL that is not having DPA. Drive the other 5 PLL inputs directly from the FPGA pin.

Altera_Forum
Honored Contributor I
184 Views

yes, i have try in this way many time, by assign those five input clk to different PIN. 

 

https://alteraforum.com/forum/attachment.php?attachmentid=14488&stc=1  

 

always show this error.
Altera_Forum
Honored Contributor I
184 Views

Could you list out the PLLs, the config of each PLL , inputs to each and outputs. I need to get a clear picture. Are the PLLs connected to global GCLK pins in FPGA?

Altera_Forum
Honored Contributor I
184 Views

In your SerDes , have you used the DPA clocks in them? To do so, you need to do the following: 

 

1. In the PLL config tun on the “Enable access to the PLL DPA output” option . The “phout” output port will be produced. The phout port is 8 bits wide. You need to re-generate PLL with Netlist option enabled after modifying.  

2. In your project directory, delete the ALTLVDS_RX .v file, then rename the ALTLVDS_RX_syn.v file to ALTLVDS_RX.v 

3. Manually edit the ALTLVDS_RX .v to make all occurances of the “rx_dpaclock” port 8 bits wide 

4. In your design, connect the PLL “phout” output to the ALTLVDS_RX “rx_dpaclock” input
Altera_Forum
Honored Contributor I
184 Views

https://alteraforum.com/forum/attachment.php?attachmentid=14489&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14490&stc=1  

 

Hi the is the PLL ipcore setting and pin assignment for those five clk input. 

thank you very much.
Altera_Forum
Honored Contributor I
184 Views

Hi 

why i cannot enable "Enable access to PLL DPA output ports" 

https://alteraforum.com/forum/attachment.php?attachmentid=14491&stc=1  

 

it there something wrong with my setting? 

 

the three output signal will be connected to serdes
Altera_Forum
Honored Contributor I
184 Views

Hi, 

 

For that, you need to Turn on the "Enable Dynamic configuration of PLL" option.
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