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Hello!:D
I am new to this forum and I came here for some support. I am a just-graduated engineer and right now I am doing an internship in Japan. My task is to develop a SMPTE time code decoder on a FPGA ALTERA DE0 TERASIC and display the time-code on the 7-segment displays. I have attended two courses at the university about digital design, but up to now I have no practical experience and unfortunately my supervisor knows nothing about VHDL. Quick summary of the theory behind the timecode:- SMPTE timecode is a set of cooperating standards to label individual frames of video or film with a time code. Timecodes are added to film, video or audio material, and have also been adapted to synchronize music. (Wikipedia: https://en.wikipedia.org/wiki/smpte_timecode )
- Timecode is encoded using LTC (Wikipedia: https://en.wikipedia.org/wiki/linear_timecode )
- The bits are encoded using the biphase mark code (also known as FM): a 0 bit has a single transition at the start of the bit period. A 1 bit has two transitions, at the beginning and middle of the period. This encoding is self-clocking.(http://www.philrees.co.uk/articles/timecode.htm )
- they are equal then the decoded value is a ‘0’
- they are different then the decoded value is a ‘1’
- How would you accomplish clock recovery on an FPGA? I look up online but I could not find any valid references. Do you have any suggestions?
- Does the Bi-Phase decoding algorithm make sense to you or you would employ another (maybe easier) solution?
- Do you think this design is feasible? Do you see any flaws or possible improvement that can be made?
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Were you successful in your Design?
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