I have been through the several hundred pages of TimeQuest documentation plus altera website examples in "TimeQuest design centre" !! to find out how to constrain my design but without any success.
In my design there are two data interfaces:
1) input data: stratix iV sends 140MHz clock to virtex to clock out bytes.
2)output data: Two DACs(I/Q) each sends its 280MHz clock to fpga to clock data out of stratix(DDR).
For both interfaces I use dc fifos for safe domain transfers.
additionally I have a 560MHz ref clock for internal PLL which produces 140/280 MHz clocks, muxed internally.
Any idea how best to constrain this design. In both cases, clock direction is opposite that of data.
Thanks.
