Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20690 Discussions

[Timing Constraints]: Binding asynchronous clock group constraint to module?

Altera_Forum
Honored Contributor II
1,048 Views

Hello, 

 

We are designing one block (similar to mega-function which is having some pre-defined logic). That block can be instantiated by end user in his/her design. We are also planning to automate timing constraints for this block so that user does not need to provide timing constraints for this. ( Many thanks to Dave and others for http://www.alteraforum.com/forum/showthread.php?t=39233 )  

 

There are 2 clocks coming into our top module and some signals are passed between these 2 clock domains. By using some synchronization techniques, we are passing the signals across these clock domains. So, we are thinking to set asynchronous clock group between these 2 input clocks coming into our Top module. It would guide time-quest not to analyze paths between these 2 clocks. This is fine for our module. But we afraid that it may lead to problem if end user is also passing some signals across these 2 clock domains in his/her module and missed to add synchronization logic for them. In such a case, time-quest will not report any timing violation and it could be hard to find out such issue. In this scenario, we can use set false path for each signals crossing clock domain in our block. But it could be lengthy process. Our question is whether it is possible to provide asynchronous clock group constraints such that it would be only considered for our block. That is, to bind that constraint to some module or something like that.  

 

Thank you for your time. 

 

Cheers, 

Bhaumik
0 Kudos
0 Replies
Reply