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Hi, During the code compilation, I get the following warning: "Critical Warning: The following clock transfers have no clock uncertainty assignment. Critical Warning: From clk (Rise) to clk (Rise) (setup and hold)" At first I got even more warning but I fixed it when constrained to 10MHz clock instead 1000MHz (system default). What does it mean and how can I fix it? (Fmax=153MHz, Setup Slack= 93.473, Hold Slack=0.670, EP3C16F256I7) Thanks, Idan
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Add the following line to your .sdc:
derive_clock_uncertainty (More recent versions of Quartus run this automatically...)
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