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Honored Contributor I
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Timing Error with RGMII Ethernet on CycloneV SoC

http://www.alteraforum.com/forum/attachment.php?attachmentid=11567&stc=1 Hi. I'm "motto" of Altera beginner. 

I want to solve the timing error message. 

 

 

Design : Cyclone V RGMII Example Design 

http://rocketboards.org/foswiki/view/projects/cyclonevrgmiiexampledesign 

 

 

Setup Timing error path : TX_CLK_OUT_125 

 

 

I am trying the below( 9 paths); 

http://www.alteraforum.com/forum/showthread.php?t=46960 

 

 

It is look like timing violation. 

 

 

I want solve timing error. Please tell me about solve it. 

 

 

If anyone has any idea, please tell me. 

Thanks in advance.
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1 Reply
Beginner
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Have you solved this issue? I have the same timing violation and could not solve it.

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