I wanted to run timing simulation for a multiplier i designed. However after successful functional simulation, the tool is giving an error while running timing simulation i.e:# ** Error (suppressible): (vsim-SDF-3196) Failed to find SDF file "Karatsuba_vhd.sdo".# vsim -novopt -c -t 1ps -sdfmax Karatsuba_vhd_vec_tst/i1=Karatsuba_vhd.sdo -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Karatsuba_vhd_vec_tst # Error loading design Error loading design Please let me know what can be done.
From the Error message it looks like you are missing the .sdo file.What device are you targeting ? Gate-level timing simulation is supported only for the Arria II GX/GZ,Cyclone IV, MAX II, MAX V, and Stratix IV device families.. Use Timing Analyzer static timing analysis rather than gate-level timing simulation. Ref: https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-handbook.pdf Page 1466 Best Regards, arslanusman2003 (This message was posted on behalf of Intel Corporation)