Timing analysis error on Asynchronous control signals

[NShan12]

Hello,

In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signals on the bus indicate Data or Address .

As the logic is checking for the edges on WRN and ALE in a process, Quartus thinks they are clocks and gives timing errors: "WRN and ALE are clocks and they are not constrained". 

How do I solve this issue having known that WRN and ALE are not clocks?

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

[sstrell]

If your code from 11/2/21 is still the same, you are still coding these signals like clocked processes instead of combinatorial logic.  You should look at adjusting your code such that the signals no longer look like clock signals to the compiler.

[NShan12]

Hello @sstrell ,

Alright. Thank you very much for your support. This issue can now be closed.