I’m trying to connect user logic to a stratix10 H-Tile phy.
For the rx and tx path I have user logic connected to the phy, driven by the tx/rx clocks provided by the phy itself. Now I want to transfer this data to system clock driving the rest of my logic. To make things simpler and because there isn’t too much logic, I decided to make my system clock the same frequency as the phys rx/tx (125MHz).
For the transfer I use a handshake logic, but sadly this results in various timing errors (rule violation and = hold slack (see picture)).
I tried setting some multi-cycle constrains, as well as asynchronous clock groups, as these clocks (to my understanding) should be unrelated.
Sadly the violations never change.
Can someone tell me what I’m doing wrong?
Also, maybe I'm reading it wrong, but doesn't the data arrive long before it is needed so why does it show an error?
User logic --- Handshake --- tx (user logic) --- tx py
user clk --- tx clk...
If you have a set_clock_groups asynchronous command, then the tool won't check that clock crossing. And as you can see, the violations are indeed for a clock crossing, since #1 they are being checked and #2 they show up as launch clock and latch clock. What are you doing for the "handshake"? That should be a fifo of some sort then, and it will include (internal, invisible perhaps) a false path so that timing is not checked.
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