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Beginner
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Timing constraints to asynchronous output

I have outputs from one FPGA to another FPGA. Outputs are clocked out of one FPGA and is completely combinational in the other FPGA. Can I set false path to these outputs.

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New Contributor III
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Yes. Set false paths to any input or output signals that you don't need the timing analyser to consider.

 

Cheers,

Alex

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Beginner
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Hi Thanks for the Reply.

 

How can we determine the signals that doesn't require timing analysis?

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New Contributor III
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Any signal in to or out of the device that is asynchronous - i.e. doesn't have an associated clock.

 

Cheers,

Alex

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Beginner
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Hi Thanks for the reply.

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