Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Beginner
43 Views

Timing error for system_soc_hps_0

I encountered the following timing error but I don't have any idea to fix this issue because I think system_sos_hps_0 is an automatically generated file from Qsys.

FPGA clock frequency setting on my design is 50MHz but it seems constraint for it is set to 100MHz.

How can I change the constraint or clock frequency to fix this timing error?

Traget device is 5CSXFC6D6F31C8.

Quartus Prime 16.0

 

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Summary of Paths ;
+--------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; -1.483 ; system_soc_hps_0:hps_0|system_soc_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2440 ; system_soc_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:dut_thru_ip_0_s_axi_rd_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; hps_0|fpga_interfaces|clocks_resets|h2f_user2_clk ; hps_0|fpga_interfaces|clocks_resets|h2f_user2_clk ; 10.000 ; -0.466 ; 10.937 ;
; -1.448 ; system_soc_hps_0:hps_0|system_soc_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2440 ; system_soc_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:dut_thru_ip_0_s_axi_rd_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; hps_0|fpga_interfaces|clocks_resets|h2f_user2_clk ; hps_0|fpga_interfaces|clocks_resets|h2f_user2_clk ; 10.000 ; -0.466 ; 10.902 ;
; -1.407 ; system_soc_hps_0:hps_0|system_soc_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2442 ; system_soc_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:dut_thru_ip_0_s_axi_rd_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; hps_0|fpga_interfaces|clocks_resets|h2f_user2_clk ; hps_0|fpga_interfaces|clocks_resets|h2f_user2_clk ; 10.000 ; -0.459 ; 10.868 ;
+--------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Path Summary ;
+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property ; Value ;
+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; From Node ; system_soc_hps_0:hps_0|system_soc_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2440 ;
; To Node ; system_soc_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:dut_thru_ip_0_s_axi_rd_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ;
; Launch Clock ; hps_0|fpga_interfaces|clocks_resets|h2f_user2_clk ;
; Latch Clock ; hps_0|fpga_interfaces|clocks_resets|h2f_user2_clk ;
; Data Arrival Time ; 18.872 ;
; Data Required Time ; 17.389 ;
; Slack ; -1.483 (VIOLATED) ;
+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

0 Kudos
0 Replies