Timing failing on just a few pins

[Altera_Forum]

Hi, 

 I'm working on a project which uses a pair of SDRAMs on a Cyclone III dev board. The design is failing timing on a few pins. I've used the TimeQuest timing report to try and figure out what's going on, and I've attached a screenshot of the report for one of the pins. The delay between IC and CELL of IOOBUF_X11_Y0_N23 seems inordinately large at over 7ns. Any hints on how I might reduce this?

[Altera_Forum]

Answering my own question for the benefit of anyone else who might hit the same issue: 

 The problem was that the pins in question are dedicated voltage reference pins. They can be used as regular IOs, but have a higher capacitance, so react slower than other pins.  The solution is to increase the drive strength on those pins.