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Altera_Forum
Honored Contributor I
774 Views

Timing failure on internal paths

Hi dear, 

 

The design failing the time on internal paths and on the same clock domain. The timing report is attached as image . This design works fine without any constraints.  

 

Can please someone explain what could be the reason and what is the solution to resolve it? 

 

Kind regards 

Mohsin
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4 Replies
Altera_Forum
Honored Contributor I
14 Views

Without seeing your design or clock constraints makes it difficult to help. 

 

The picture shows a long data delay so perhaps you have too much logic on those paths. No way to know for sure.
Altera_Forum
Honored Contributor I
14 Views

Looks like you have a large fan-out path thats causing the timing violations. In any case, can you describe what you're designing and also put in the constraints etc here so we can take a look at it.

Altera_Forum
Honored Contributor I
14 Views

Hi, 

 

Thank you for your reply, 

 

I have not written the design, the person who have written this code is retired now. I have written a short description of the design attached as pdf file and also the constraints which I have written are also attached. 

 

I want to increase the speed / frequency of algorithm. The algorithm in design is working fine at 164MHz clock without any constraints and I was able to run it at 190MHz with the attached constraints.  

 

Please let me know if you need further information.
Altera_Forum
Honored Contributor I
14 Views

Your original screenshot is missing the most important bits. 0 to 8 ns is just setting the stage. 8 to 15 is where the real action is. 

 

Also, you seem to be contradicting yourself. If it is working fine at 164 without any constraints and you were able to run it at 190 with the constraints, then how come your screenshot is showing a failure (-1.5 ns setup slack) at 172 MHz (1/5.814 ns)?  

 

Post the view of the second half of the timing path and the drawing in the "extra fitting information" tab.
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