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Altera_Forum
Honored Contributor I
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Timing for MAX 10 ADC Control Core Only interace logic

I'm trying to create the necessary external logic to control a MAX10 ADC Control Core Only instance. The timing in figure 8 of the UG-M10ADC User Guide does not define the relationship between command_valid, command_startpacket, command_endofpacket, or command_ready. Also, what is the reference for the term "ADC soft IP clock"? Is this the same thing as "modular_adc_pll_clock"?

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Altera_Forum
Honored Contributor I
134 Views

Hi, I'm only just learning this myself, and it's taken me the best part of 3 weeks to get it simulating, so take my input with caution. 

 

1) I think the two clocks can be separate. The PLL clock has to come from the PLL whether you want it to or not. The other clock could be a different frequency. Say, 8MHz for the logic, and 2MHz for the PLL. I'm using the same clock for both. 

 

2) I don't think command_startpacket, command_endofpacket are relevant for the Core Only ADC, or at least I've not found a use yet. I have them tied low. 

 

3) command_valid seems to be the important signal. It seems that when you take it high and HOLD it high, some time later command_ready pulses high for one clock. (I assume this is the IP clock). Thereafter command_ready and response_valid pulse high both pulse high together for one clock, at the rate you selected when you created the IP core. response_channel() and response_data() are both valid for one clock at the same time as response_valid. 

 

4) It appears you can change command_channel on the fly.
Altera_Forum
Honored Contributor I
134 Views

I'm running into the same problem and I would love to find someone who has a VHDL file that correctly instantiates the Max 10 ADC. I would also like to have some sharp words with whoever thought it was a good idea to make it a Qsys only component. 

 

I have a Max 10 ADC watching 9 analog signals - 4 power supplies and 5 actuator FET monitors. The logic is dead simple - really just a set of digital comparators with hysteresis. What I want from the ADC is set of 9 12-bit values and an update signal to tell the downstream logic a new sample set is ready. 

 

Even a simple example of how to instantiate and drive this thing in VHDL would be great, as I have tried everything I can think of. Quartus knows it is supposed to be there too, as it shows up in the hierarchy.
Altera_Forum
Honored Contributor I
134 Views

Hi, (note following update post about clocks) Attached is a vhdl file that I got working. I cut it down a bit, so can't guarentee it'll compile first time, but the gist is there. Is reads 2 channels periodically, using the raw version of the ADC. ADC and PLL generated using Quartus 16/17 Tools->IP Catalog. PLL converts 8MHz to 2MHz, and is there only because the ADC won't work without the PLL. The BIG problem I had was what an Altera FAE has confirmed to me is a bug in Quartus: the IP core Wizard for the ADC generates 2 sets of files: a simulation folder and a synthesis folder. Only the SYNTHESIS ADC folder contains the IP Core customisations you specified - the simulation folder just contains a blank ADC template, which naturally does not simulate. Currently I'm compiling the synthesis files manually in ModelSim, but a simpler way would likely be to just copy the synthesis files into the simulation folder. Hope this helps, Rob

Altera_Forum
Honored Contributor I
134 Views

 

--- Quote Start ---  

Hi, Attached is a vhdl file that I got working.  

--- Quote End ---  

I need to post an update to this! The code I posted above works in simulation (once you get past simulation tools problems), but does NOT work in hardware. Issue: The ADC does not work if the two input clocks into the ADC are the same clock! Solution: use a different clock, or just invert the clock_clk clock.
Altera_Forum
Honored Contributor I
134 Views

Thanks, for the code. I am having the same problem. The documentation could always be better. I will post wiring and timing diagrams when I get mine working. Currently the ADC output is all zero's.

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