Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20880 Discussions

Timing for Quartus Multiply .BDF module

John-Monahan
Beginner
673 Views

I am using a large number of Quartus IP LPMMULT "Basic Functions" both in parallel and then in series to calculate a 32 bit number from a large number of 16 bit (unsigned) array of numbers.

JohnMonahan_0-1692651878927.png

Its a large branched tree. I assume each multiplication takes place with a low to high clock pulse. How do I know when the calculation is done to issue a clock pulse to the next adder using a pair of result[31..0] values from the previous multiplier.
---->Mult---->Mult---->Mult
|
---->Mult--->Mult----
|
---->Mul--->
Any help here from an expert would be appreciated -- I'm new to Quartus.

PS this may be the wrong location for this question, if so where is best.

 

Labels (1)
0 Kudos
3 Replies
JesusE_Intel
Moderator
651 Views

Hi John-Monahan,


I have moved your question to the programmable devices board for better assistance.


Regards,

Jesus


0 Kudos
FvM
Valued Contributor III
634 Views
Hi,
lpm_mult has a configurable latency (e.g. one clock cycle) it's set in Megawizard.

Don't know how you arrive at 32 bit output for 8x8 multiply?

lpm_mult IP supports up to 256×256 multiply in so far there's no need in cascading multiplier blocks manually.
0 Kudos
John-Monahan
Beginner
621 Views

I have a large number of 8 bit paired inputs which I later all add together. Essentially a large matrix dot product.

 

0 Kudos
Reply