Hi all, a common way I see pipeline architectures in devices such as the Tofino 3 switch that contain MAU units defined is each MAU has x TCAM blocks and y SRAM pages. Are the x and y amounts of TCAM/SRAM referring to the amount available solely for the key portion of a key, action, action data table? As an example, if an MAU is described as having 100 SRAM pages available and my algorithm will use 100 SRAM pages worth of keys + additional 20 pages for the action data, is that fine? Or will the action data SRAM amount also need to be factored in so that the key+action data will not exceed 100 pages total?
Also, I was wondering if there was a way to find out specific Tofino 3 specs such as the number of MAUs per pipeline and the amount of TCAM blocks/SRAM pages that they each hold?
Tofido 3 seems to be a Asic Product, https://stordis.com/blog/open-networking/what-is-intel-tofino-main-benefits-use-cases/
Can you take a look in https://community.intel.com/ to see if there are suitable area for you to raise question?
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