Tofino 3 Details/Match-Action Table Clarification

[ThePuriProdigy]

Hi all, a common way I see pipeline architectures in devices such as the Tofino 3 switch that contain MAU units defined is each MAU has x TCAM blocks and y SRAM pages. Are the x and y amounts of TCAM/SRAM referring to the amount available solely for the key portion of a key, action, action data table? As an example, if an MAU is described as having 100 SRAM pages available and my algorithm will use 100 SRAM pages worth of keys + additional 20 pages for the action data, is that fine? Or will the action data SRAM amount also need to be factored in so that the key+action data will not exceed 100 pages total?

Also, I was wondering if there was a way to find out specific Tofino 3 specs such as the number of MAUs per pipeline and the amount of TCAM blocks/SRAM pages that they each hold?

Thank you!

[Kenny_Tan]

Hi,

Is this related to FPGA question?

Thanks,

Best regards,

Kenny

[ThePuriProdigy]

I'm new to the forum. Where would this question regarding Tofino 3 go? I saw other tofino-related questions under FPGA.

-Best,

Puri

[Kenny_Tan]

Tofido 3 seems to be a Asic Product, https://stordis.com/blog/open-networking/what-is-intel-tofino-main-benefits-use-cases/

Can you take a look in https://community.intel.com/ to see if there are suitable area for you to raise question?

[Kenny_Tan]

As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.