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HBhat2
New Contributor I
433 Views

Transceiver speed grades

Hi,

 

Targeting to use Stratix 10 SX SoC FPGA for an application which includes transceiver working at ~22Gbps per channel. Such 4 to 8 lanes (both TX and Rx) may be there in use at a time. Initially thinking of using Stratix 10 SoC dev kit for Proof of concept. Here, my concern is the transceiver seed grades. I gone through the document and understood that the '1' is the fastest and 3 is the slowest in family. I understand the FPGA fabric speed grade, but unable to visualize the impact of Transceiver speed grade. Can anybody share more details on transceiver speed grades?

 

With Regards,

HPB

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4 Replies
BJona
Novice
93 Views

Hi,

That's a good question. If you look at s10 SX/GX device overview datasheet and the part used in the s10 soc board(1SX280U) the X means that there are transceivers working at 28.3Gbps maximum.

GXT channels can achieve this, and GX ones can run up to 17Gbps.

In the manual of the demo board, there are 8 GXT Channels on FMCA port and 8 other GXT channels on FMCB.

I guess you will have to buy a FMC daughter card with SMA connectors for your test bench.

Also, have a look to stratix 10 datasheet, everything is explained about transceivers (E-Tile, H-Tile and L-tile)

Hope it helped,

regards,

John

HBhat2
New Contributor I
93 Views

image.pngHi John,

 

Thank you for the info. and asking me to go through the transceiver userguide. I found the table briefing about the impact of speedgrades.

 

Wit Regards,

HPB

CheePin_C_Intel
Employee
93 Views

Thanks lot John for the explanation.
CheePin_C_Intel
Employee
93 Views

Hi HPB, Regarding your inquiry on the documentation in another thread "hat are the exact definitions of chip-to-chip, chip-to-module and back-plane applications?", it seems like I am unable to post to that thread. Thus, I am adding my response to your latest inquiry here for your visibility. Sorry for the inconvenience. As I searched through the existing documentation ie handbook and user guide, seems like I am unable to locate any specific document which explain in further details on the definition of the interconnect interfaces. I think you might want to search in web to see if you could find any detailed description as reference. Sorry for the inconvenience. Best regards, Chee Pin
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