I'm using transceivers to transfert 32 bits from a cyclone V to a cyclone IV
Parralel clock is set to 100MHz, and I use 2Gbps with 2 transceiver channels to send data.
Currently, to test, I set the rx_seriallpbken to "11" to put the loopback from RX to TX in cyclone V.
I'm usign the 8b/10b encoder with automatic word alignment (sync_sm), with 17C alignment pattern.
Sending "BCBCBCBC" regularly, alignment is always OK but only on one channel, never on the second.
I expected to have the "BCBCBCBC" at the same time...
So, do I miss something for the word alignment / channel alignment ?
I join two screenshot of the Signal Tap Logic Analyser, and the configuration of the Transceiver
PS : by the way, the Cyclone IV decodes and align correctly the data form the 2 channles of the cyclone V.
Sorry for the delay. As I understand it, you observe some alignment issue with one the XCVR channel in CV device in serial loopback mode. As I look at the signaltap screenshot, it seems like the CH0 is not aligned properly. To facilitate the debugging, would you mind to do the following:
1. Focus on the CH0, send repeated fixed pattern ie control character 0xBC + a dummy data. You might want to configure the byte ordering according to the dummy data.
2. Enable the seriallpbk for CH0, then monitor if the word alignment achieved?
3. If CH0 can achieve alignment, add on similar steps to the CH1.
Please let me know if there is any concern. thank you
I moved to manual alignment, using the the internal loopback of the transceiver for test.
The TX send K28.5 D16.2 / K28.5 D17.2 / K28.5 D18.2 on the channel 0 and the same pattern on the channel 1 after.
I start the alignment on the channel 0 and wait for the syncstatus change.
Expected value on receiver will be (in hexa) 0xBC50 - 0xBC51 - 0xBC52.
But I observe something different, I receive 0xBC50 - 0xBC53 - 0xBC50, even if the syncstatus is asserted.
I've no problem with the 2nd channel (data on 31-16).
Thanks for your help.
Thanks for your update. As I understand it, you have enable the internal serial loopback but still observe incorrect value at the RX data output. with serial loopback, we can isolate out signal integrity related issue. Since the sync status is asserted, the word alignment has achieved correct word boundary. As I look at the data, seems like there is 1 bit flipped ie 51 vs 53. This is something not expected under serial loopback condition.
If I understand it correctly, you are using signaltap to monitor the data. One of the possible causes to this might be timing problem with signaltap. Can you try the following:
1. Increase the sampling clock of the signaltap to see if it helps. Ideally you should try to increase the sampling clock to at least 2x of the parallel data frequency.
2. Create a design with only single channel. Repeat the test to see if there is any difference?
3. Can you send constant data ie 0xBC51 to see if there is any difference?
Please let me know if there is any concern. Thank you.
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.