Showing results for 
Search instead for 
Did you mean: 
Honored Contributor I

Transfering data from FPGA into HPS with one-port-RAM in DE0-nano-soc.




I am a newbie in digital design and just started to study this field. I own an DE0-Nano-SoC board and after some experiments with Verilog and FPGA part I want implement such design which read the values from the ADC and store they into the memory in FPGA part and simultanously read this memory in HPS and process in C-written program. And then probably send via network interface. 



I implemented the driver to work with the ADC and some other modules in Verilog and a top level entity in BDF, inserted an IP-core for one-port-ram and inserted the block entity of it into my top-level BDF, connected the memory with my driver and so on. 

Then I launched Qsys, inserted the HPS and one-port-RAM from the catalogue, conncted the LW bridges, the clocks and the resets and generat the Verilog files. 



Then I was executed the TCL scripts that was generated by Qsys. hps_sdram_p0_parameters.tcl was OK and I performed Analysis and sintesis after it succesfully. But when I launched _pin_assignments.tcl I got an error with the message that sdram is never instantiated. 



Could anybody explain how such projects must be organized step by step? The example that Terasic provide with the board is not very clear because a lot of important steps were skiped and also it shows usage not of the memory but of PIO. 

After reading many altera's documents I stll can't understand how to use the same memory in FPGA and HPS because of the complexity of the EDA and the device itself. Maybe somebody knows any examples of the projects with interconnection betwin FPGA and HPS that could help me?
0 Kudos
1 Reply
Honored Contributor I


I want to do the exact same, but couldn't find any help online. 

I know it's been a while, but did you manage to do what you wanted, and if so, do you happen to still have your design ? I could really use some help here ... 

Thanks in advance