Triple speed example design for Cyclone V GT dev kit - Intel Community

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Triple speed example design for Cyclone V GT dev kit

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The board update portal example project use ETH but use old Quartus version and It can't build meeting timing constraint.

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HI,

Feel free to check out below other 2 Cyclone V TSE reference design link.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an647.pdf

https://fpgacloud.intel.com/devstore/platform/14.0.0/Standard/triple-speed-ethernet/

Thanks.

Regards,

dlim

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