Tutorial or user guide on simulating HPS-FPGA system

[Altera_Forum]

Hi, 

 Does anyone know if I can find any tutorial or user guide on how to use Modelsim-Altera to simulate an HPS-FPGA soc? I'm able to use vlog to compile the design, however, when I do vsim, many design units cannot be found. This includes: cyclonev_hps_peripheral_sdmmc, cyclonev_hps_peripheral_sdmmc, cyclonev_hps_peripheral_usb, etc.  I haven't seen any document about simulating an HPS-FPGA system. Is it ever possible? I am using the modelsim-altera with license (modelsim-ae). Is there any other license that I need? Thanks!  Qinru

[Altera_Forum]

Hi, 

 Check below link. https://www.altera.com/support/support-resources/design-examples/design-software/qsys/exm-hps-axi-bfm.html  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Thanks. It compiles okay. However, I got error loading the design. There are lots of warning about fail to find the design. For example: 

 # ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_hist_dump' in DPI precompiled library search list "C:\intelFPGA\18.0\ip\altera\mentor_vip_ae\common/questa_mvc_core/win32_gcc-4.2.1/libaxi_IN_SystemVerilog_MTI_full.dll ".   There is also error message in the command line:   C:\intelFPGA\18.0\modelsim_ae\win32aloem>vsim -mvchome C:\intelFPGA\18.0\ip\altera\mentor_vip_ae\common   Reading C:/intelFPGA/18.0/modelsim_ae/tcl/vsim/pref.tcl 'env' is not recognized as an internal or external command, operable program or batch file. terminate called after throwing an instance of 'std::bad_alloc'  what(): std::bad_alloc  Then the program got terminated.        --- Quote Start ---  Hi,  Check below link. https://www.altera.com/support/support-resources/design-examples/design-software/qsys/exm-hps-axi-bfm.html  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)  --- Quote End ---  

[Altera_Forum]

Hi, 

 In the above link, the example uses the Mentor Graphics* Master bus functional model (BFM) to model the HPS AXI Bridge interface communicating with the FPGA core logic. Which required License kindly check the below link table-1 to generate the required(AXI BFM) license and try to simulate. https://www.altera.com/products/intellectual-property/design/ip-base-suite.html  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)