USB blaster II pin 6 and 8 & HPS TRST, nRST pins

[Altera_Forum]

Hi, I need some advice on the USB blaster II pin 6,8 and the hps reset signals.  

We found that the ds5 debugger via USB blaster II does not connect everytime, and also after the hps loaded preloader, U-Boot via QSPI (bare metal), the ds5 do not connect so that we can step code. (After device was flashed and we want to step code with ds5) MSEL set to FPP, and we use SPL and or U-Boot to load FPGA via FPGA manager.   We suspect problem on reset.  Is the USB blaster pin 6 input or output? Is it open collector?  Pin 8 is according to the USB blaster II document for jtag not connected, however I see in several dev kit sch that pin 8 is connected to hps trst??  In one sch, pin 6 is connected to hps nRST, and connected to push button via debouncer. Is the USB blaster II reset from this push button, or does the USB blaster II provide a output reset signal to hps NRST? Then we will have 2 driving circuits??   The question is, how should I connect the hps resets, blaster pin 6,8? nPOR is connected to a proper watchdog.   My current test pcb does have link via not fitted 0R resistor between pin 6 and hps nRST. Hps bank 3v3, and blaster target voltage 2.5V.Hps nRST also have a pull up resistor to 3V3. If I insert the not fitted resistor, should I remove the 3v3 pull up, or change the blaster target voltage from 2.5 to 3.3? If I remove the pull up, easiest then I guess pin 6 will reset hps via nRST on command from ds5,(and probably solve our connection problem) but with USB blaster not fitted nRST is floating?   I am using a Cyclone V SOC Thanks in advance.

[Altera_Forum]

Make sure you are not running in the "HPS Tap Controller Is Reset By Cold Reset" erratum: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/es/es-01042.pdf 

 This document has I/O descriptions including the HPS JTAG and reset I/O: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-v/pcg-01014.pdf

[Altera_Forum]

Hi Thank you for the reply. 

 I can comment the following, to maybe help other people. Pin 6 of the USB Blaster II must be connected to HPS_nRST. (VCC IO Bank & JTAG in my case is both 3V3). If you do not connect this blaster reset to the HPS nRST, the DS5 will not always connect & when inspecting global variables it will take fore-ever to update the DS5 screen with global variables after each step of stepping the code with F6. I changed my board to connect pin 6 to HPS_nRST, and now DS5 is working like a dream (connection and Global variable inspection)  I tested XJTAG successfully with my board, without have pin 8 of the USB Blaster connected to HPS_nRST. So this does not seem to be i definite requirement for XJTAG, however in future boards i will make provision to connect pin 8 to HPS_nRST via not fitted 0R resitor.  Thanks