Unable to establish a link of RapidIO

[晓郝]

When I use RapidIO in Arria 10 to communicate with DSP , I find port_initialized of IP core is high , but the port_ok of the port 0 error and status CSR-offset:0x158 is low. According to RapidIO Gen1 Debug Checklist of INTEL FPGA WiKi , I check the steps of Unable to establish a link , but the issue still exist.

[Nathan_R_Intel]

Hie, Can you help clarify if your design is unable to establish a link although CSR 0x158 = 0 and port_initalized goes HI? Regards, Nathan

[晓郝]

Hi,

When DSP complete the initialization, the port_initialized of FPGA IP core is high, but CSR 0x158 = 1 ,

the PORT_UNINIT of this register is 1, the PORT_OK of this register is 0 . Besides I find  the

no_sync_indicator is 1. What maybe  bring on unable to establish a link.

Tah

[Nathan_R_Intel]

Hie Tah, Some of the reasons for cannot establish link is already provided in the Intel FPGA Wiki section below such as link partner does not match core configuration, core in reset, timing no met, incorrect analogue settings etc. https://fpgawiki.intel.com/wiki/RapidIO_Gen1_Debug_Checklist#Unable_to_establish_a_link Hence, please check the other checklist questions related to link cannot establish. Regards, Nathan

[晓郝]

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[晓郝]

​hi,

OK, I will check that again.

Thanks.

[Nathan_R_Intel]

Please advice if issue is resolved. Regards, Nathan

[ghe001]

楼主，问题解决了没？我也遇到同样的问题，能否共享一下解决办法，谢谢。