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Altera_Forum
Honored Contributor I
1,304 Views

Unable to simulate MAX 10 ADC

Hi, 

 

I'm thoroughly stuck on simulating the MAX 10 ADC. 

Tools: Quartus 17 Lite (and 16.1) + ModelSim-Altera 10.5b 

 

Modelsim error: 

# ** Error: (vsim-3033) C:/temp/ADCtest3/source/On_Chip_ADC/simulation/submodules/On_Chip_ADC_modular_adc_0.v(38): Instantiation of 'On_Chip_ADC_modular_adc_0_control_internal' failed. The design unit was not found. 

 

Steps taken: 

1. Create Max10 project with top level and testbench VHDL. 

2. Use IP Catalog to create "Altera Modula ADC Core" and generate the HDL code, selecting VHDL synthesis and VHDL models. 

3. Add the generated component to my VHDL 

4. Add the generated .qip and .sip files to Project Navigator 

5. Tools>Run Simulator Tool>RTL Simulation 

6. Get several ModelSim error messages similar to the above. 

 

I'm puzzled that I don't see 'On_Chip_ADC_modular_adc_0_control_internal' defined anywhere. 

 

Does anyone know what causes this error? 

 

(I'm using the IP Catalog, not Qsys, because I want to be able to wire up the ADC PLL myself. I do have the PLL.) 

 

Thanks, 

Rob
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3 Replies
Altera_Forum
Honored Contributor I
68 Views

Hmm, no replies here. 

 

And the support case I raised seems to have stalled when the suggested solution of adding a zip-load of extra files to the Quartus installed libraries and then compiling in ModelSim instead of using NativeLink produced the same error message. 

 

So... nobody has ever succeeded in simulating a MAX10 ADC?
Altera_Forum
Honored Contributor I
68 Views

Did you added the testbench in Nativelink ?  

 

What is the vsim command executed by Modelsim, did it included the libraries with -L switch ? 

 

Best Regards, 

arslanusman2003 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
68 Views

Hi,  

 

I had the same issue few month ago.  

 

There are mistakes in Altera simulation model (regarding module's naming) and I simply linked the synthesis model in my simulation and it worked. 

 

Source the files C:/temp/ADCtest3/source/On_Chip_ADC/synthesis/... instead of C:/temp/ADCtest3/source/On_Chip_ADC/simulation/... 

 

Excelsium