UniPHY LPDDR2 Controller Memory Clock Rate

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

UniPHY LPDDR2 Controller Memory Clock Rate

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While LPDDR2 devices are specified to work down to 10Mhz for low power operation, the UniPHY Controller IP allows a minimum of 166Mhz (presumably the minimum for "normal" DDR2 devices). Is there an easy way to get the controller to operate below 166Mhz?

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