Unused Agilex F Tiles and recovered clk output.

emrahener · ‎11-17-2022

Hi,

We are using AGIB027R31B2E2V on our digital board design. We are using FHT13C but not using FHT13A. Pin Connection guideline says Tie to GND if there is no FHT channel used for the following pins

VCCEHT_FHT_GXF[L,R], VCCERT1_FHT_GXF[L,R], ,VCCERT2_FHT_GXF[L,R], VCC_SENSE_FHT_GXF

VSS_SENSE_FHT_GXF

which is a different wording compared to `Tie to GND if this tile is not used` used for regulator F tile supplies.

VCC_HSSI_GXF[L,R], VCCH_FGT_GXF[L,R] , VCCERT_FGT_GXF[L,R], VCCFUSECORE_GXF[L,R]

VCCFUSEWR_GXF[L,R], VCCCLK_GXF[L,R]

Should we connect VCCEHT_FHT_GXF_13A , VCCERT1_FHT_GXF_13A , VCCERT2_FHT_GXF_13A,

VCC_SENSE_FHT_GXF_13A,VSS_SENSE_FHT_GXF_13A since we are still using 13C and the guideline says `if there is no FHT channel used`

Should we connect ENB_GXF_FHT13A to GND and ENB_GXF_FHT13C to VCC ?

Another question is on recovery clock output for F tiles. Is there a specific reason to have them from clk pins instead of routing them through fabric ? Is there a rule for their pin assignment when used for links with more than 4 differential pairs? Is it at the same frequency with the data rate? Is it LVDS?

Should we connect I_PIN_PERST_N_GXF to GND if F Tile is used but not as PCIE ?

AqidAyman_Intel · ‎11-22-2022

Hi,

You can follow the guidelines inside the document. If you are using FHT channel, then connect the pins as per suggested.

emrahener · ‎11-22-2022

My questions are on unclear statements on guideline.

13A and 13C has separate supply and ENB_GXF_FHT inputs. We are using All FHT13C but not using any FHT13A Rx/Tx. Guide line says if there is no FHT channel used. Given this fact can we connect 13A supplies and ENB_GXF_FHT input to GND?

Should we connect I_PIN_PERST_N_GXF to GND if F Tile is used but not as PCIE ? This is not directly specified.

Another question is on recovery clock output from F tiles. Is there a specific reason to have them as output from clk pins instead of routing them through fabric ? This is a question to minimize test connector cnt on out design If we can route the recovery clk through fabric I will mux recovery clk from multiple links inside FPGA and observe them on a single external connector. Is there a rule for their pin assignment when used for links with more than 4 differential pairs? Is it at the same frequency with the data rate or with the reference clk input? Is it LVDS?

AqidAyman_Intel · ‎12-01-2022

Hi,

You can treat each tile on the device as a totally independent from each other. So, any unused XCVR tile can be connected to GND. In your case is FHT13A. As for I_PIN_PERST_N_GXF, it just depends on the usage of PCIe, it should not impact the ethernet links.

Regards,

Aqid

AqidAyman_Intel · ‎12-08-2022

As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

emrahener · ‎12-09-2022

Hi Aqid,

Thanks for the replies. There is only one open point in the ticket regarding the recovery clk. For the two other issues I have no further questions.

`Another question is on recovery clock output from F tiles. Is there a specific reason to have them as output from clk pins instead of routing them through fabric ? This is a question to minimize test connector cnt on out design If we can route the recovery clk through fabric I will mux recovery clk from multiple links inside FPGA and observe them on a single external connector. Is there a rule for their pin assignment when used for links with more than 4 differential pairs? Is it at the same frequency with the data rate or with the reference clk input? Is it LVDS?`

Kind Regards

Emrah ENER