Usage of out-of-bank fractional PLLs for HSSI transmitter channel clocking

[FRoth]

We are using Arria 10 with 480K LEs in F34 package device which also has 12 fractional PLLs. Eight of these fPLLs are located in standard transceiver banks, but four fPLLs are located outside of any transceiver bank.

Is it possible to use the out-of-bank fractional PLLs for HSSI transmitter clocking? Is there any clock network capable of delivering the high speed clock across the side of the device? Is it possible to use xN clock network for this purpose (does it have sufficient span)?

[Nathan_R_Intel]

Hie, F34 package refers to the pin count of 1152 which comes in either 24 transceiver channels or 36 transceiver channels. Since you only have 8 fPLL in transceiver banks, I will assume your device has 24 transceiver channels. Please correct me if I am wrong. You may refer to your part number and determine the amount of transceiver channels from the "ordering code - Pg 8" of following document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_overview.pdf Please check my replies to your questions: Is it possible to use the out-of-bank fractional PLLs for HSSI transmitter clocking? If you are looking to use the out-of-bank fractional PLL (fPLL) as a Transmitter PLL, the answer is "NO" you cannot. The out of bank fPLL cannot be used as a HSSI Transmitter PLL. You can use the out of bank fPLL to provide the reference clock or cascaded to another fPLL or ATX PLL within the transceiver/HSSI banks. Is there any clock network capable of delivering the high speed clock across the side of the device? No, none of the high speed clock line (x1, x6, xN) can deliver high speed clock across the side of the device. However, for a 24 channel device; transceiver channels are only located on one side. The xN clock line is spanned across this 24 channels; hence you don't need to across to the other side. Is it possible to use xN clock network for this purpose (does it have sufficient span)? No the xN clock network only spans across the transceiver bank. The xN clock line of a particular side only spans across channels on one side. However, the usage of xN clock line is limited to maximum 30 channel span. This is documented in our user guide (Pg 388-Figure 179). https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf The xN clock network also does not span to out-of-bank fPLL. Regards, Nathan