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Honored Contributor I

Use locked signal from PLL as reset

Hi guys, 

I have some troubles by using a PLL in combination with a Qsys (HPS) system. 

On the arria10 development board, I try to increase the fpga clock (100MHz) with a PLL to 200MHz. 

For this, I instance a PLL from the IP Catalog. The 'refclk' is the 100MHz clock and the 'rst' signal is the fpga reset signal (from a button). 

I connect the outclk_0 (200MHz) to the Qsys component which includes a HPS and some other peripheral. I like to use the Avalon Bus in the 200MHz clock domain. 

After the synchronisation from the PLL 'locked' signal, I added the signal as reset to the Qsys component. 


Now, in the TimeQuest Analysis, I become a Recovery error on the reset signal. I saw, that Qsys added a "altera_reset_controller" block which include also a "altera_reset_synchronizer" block. 

In my designe, the timing violation is between this sync block ('altera_reset_synchronizer_int_chain_out' signal) and some Qsys component. 


Do somebody know why I receive this timing issue? By the way, when I use directly the external reset (from the button) the timing closure.. But in this case, I didn't checked the start up from the PLL... 


Thanks for your help and best regards, 

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Honored Contributor I

Now I have a solution to my issue: 

The problem was, that the external clock pin was close to the left bottom edge. In this case, a PLL close to the pin was selected. 

Then, the clock output from the PLL and the synchronized reset signal was connected to a global clock network on the left bottom edge. 

The other logic and devices from the HPS was located on the top edge from the FPGA. This distance (between top and bottom of the FPGA) is too large to close the timing... 

When the PLL location is explicitly set to the center of the device, it works fine with 200MHz. I did a assignment for the specific PLL in the Assignment Editor to a specific location. Something like this: 

To: PLLExample:u0|PLLExample_altera_iopll_160_khuhuhq:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst 

Assignment Name: Location 

Value: IOPLL_X78_Y114_N1